* Hi. I'm struggling to get DMA writes to take on STM32 SPI. Reads and writes aren't taking effect. Here's the process. I've removed most of the comments and feature-gating:

Program code:
```rust
    spi.enable_dma(&mut dma);

    let mut write_cmd = [0x80_u8, 0b01000001];
    let mut read_cmd =  [0_u8; 2];
    let mut xmit_buf = DmaWriteBuf { buf: &write_cmd }; // Buffer to request a read of the config data.

    cs.set_low();
    spi.write_dma(&mut xmit_buf, &mut dma);
    // Delay as a debugging, shim to allow for CS to stay low until
    // write is done, and not read until write is done.
    delay.delay_ms(50);
    cs.set_high();

    // Do a normal, non-DMA read command, which we know works.
    cs.set_low();
    spi.transfer(&mut read_cmd);
    cs.set_high();
    // This shows the DMA write not taking effect; shows previously-set reg value.
    defmt::info!("CFG REG: {:?}", &read_cmd);
```

Simplified `Spi::enable_dma` code:
```rust
    pub fn enable_dma(&mut self, dma: &mut Dma) {
        self.regs.cr1.modify(|_, w| w.spe().clear_bit());
        self.regs.cr2.modify(|_, w| w.rxdmaen().set_bit());
        self.regs.cr2.modify(|_, w| w.txdmaen().set_bit());
        self.regs.cr1.modify(|_, w| w.spe().set_bit());

        // todo: These are only valid for DMA1!
        // (Code here that does Channel Select, which is uniqueish to L4)
    }
```

Simplified `Spi::write_dma` code:
```rust
    pub fn write_dma<B: embedded_dma::WriteBuffer>(&mut self, mut buf: &mut B, dma: &mut Dma) {
        let (ptr, len) = unsafe { buf.write_buffer() };

        let channel = match self.device {
            SpiDevice::One => dma::DmaChannel::C3,
            // ...
        };

        let periph_addr = &self.regs.dr as *const _ as u32;
        dma.cfg_channel(
            channel,
            periph_addr,
            ptr as u32, // mem addr
            len as u16,
            dma::Direction::ReadFromMem,
            ChannelCfg::default(), // Auto-incr mem but not periph, med pri, 8-bit data-size etc.
        );
    }
```

I can post what `cfg_channel` etc does if that would help. Am I missing any key steps?
How does CS work on SPI dma? Do you need to set it high in an ISR etc? Thank you