sboyd: Any idea where vals for hfpll were taken from?
i see 
https://github.com/torvalds/linux/blob/master/drivers/clk/qcom/hfpll.c#L23
i guess it was written with qcs405 in mind but downstream sources have no place in qcs405 clk cpu driver where it writes this and noticed 8974 and 8976 both have
PLL_CONFIG_CTL RESET_VALUE 0x04D0405D
+ there is a lot of missleading in downstream sources where main difference between SR/HF is just that one writes reset after waiting few seconds.
Later on qcs405 android sources inside clk-pll lists SR2 as enable ops for hf.