I don't know if this sort of content is acceptable in the chat, but I've been thinking about the M1 cores and wanted to share some thoughts I've had. Pure speculation ofc!

Anandtech's uArch testing[1] suggested the M1 ROB is something like 600+ deep. Correspondingly the reg rename stations were similarly huge with ~350 entries for INT and FP each.

Considering that this is a power efficient SoC and these elements of OoO hardware are traditionally considered "power hungry", this is unusual.

So I wonder if they've done something quite similar to Mitch Alsup's work based on the CDC 6600. Ikcl states that the fully featured OoO scoreboard implementation avoids a CAM entirely[2]. It also seems to me that such a design is well suited towards such a wide CPU.

What do you guys think?

[1] https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2
[2] https://libre-soc.org/3d_gpu/architecture/6600scoreboard