[    0.393875] arm-smmu 1c40000.iommu: SMMUv2 with:
[    0.393906] arm-smmu 1c40000.iommu: stage 1 translation
[    0.393933] arm-smmu 1c40000.iommu: stage 2 translation
[    0.393961] arm-smmu 1c40000.iommu: nested translation
[    0.393987] arm-smmu 1c40000.iommu: address translation ops
[    0.394015] arm-smmu 1c40000.iommu: non-coherent table walk
[    0.394044] arm-smmu 1c40000.iommu: (IDR0.CTTW overridden by FW configuration)
[    0.394080] arm-smmu 1c40000.iommu: stream matching with 4 register groups
[    0.394116] arm-smmu 1c40000.iommu: 4 context banks (0 stage-2 only)
[    0.394424] arm-smmu 1c40000.iommu: Supported page sizes: 0x63315000
[    0.394459] arm-smmu 1c40000.iommu: Stage-1: 48-bit VA -> 32-bit IPA
[    0.394491] arm-smmu 1c40000.iommu: Stage-2: 32-bit IPA -> 32-bit PA
[    0.394523] arm-smmu 1c40000.iommu: found only 3 context irq(s) but 4 required