[ 2.376086] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.376091] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.376095] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.376100] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.376104] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.376108] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.376123] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.376128] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.376133] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.376137] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.376163] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.376303] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.376331] [drm:dsi_cmds2buf_tx] ret=50 [ 2.376339] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.376349] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.376360] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.376384] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.376389] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.376393] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.376397] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.376402] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.376406] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.376410] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.376414] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.376418] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.376433] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.376438] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.376442] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.376446] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.376471] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.376611] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.376638] [drm:dsi_cmds2buf_tx] ret=50 [ 2.376647] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.376657] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.376668] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.376692] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.376697] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.376701] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.376705] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.376710] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.376714] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.376718] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.376722] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.376726] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.376741] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.376747] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.376751] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.376755] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.376781] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.376921] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.376949] [drm:dsi_cmds2buf_tx] ret=50 [ 2.376958] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.376967] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.376979] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.377002] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.377007] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.377011] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.377015] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.377020] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.377024] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.377028] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.377032] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.377036] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.377051] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.377057] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.377061] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.377065] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.377091] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.377231] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.377259] [drm:dsi_cmds2buf_tx] ret=50 [ 2.377267] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.377276] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.377287] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.377310] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.377315] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.377319] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.377323] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.377327] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.377331] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.377335] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.377340] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.377344] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.377359] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.377365] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.377369] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.377373] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.377399] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.377539] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.377567] [drm:dsi_cmds2buf_tx] ret=50 [ 2.377575] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.377586] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.377597] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.377620] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.377625] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.377629] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.377634] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.377638] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.377643] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.377647] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.377651] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.377655] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.377670] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.377675] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.377679] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.377684] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.377709] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.377850] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.377877] [drm:dsi_cmds2buf_tx] ret=50 [ 2.377886] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.377896] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.377907] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.377930] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.377935] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.377940] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.377945] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.377949] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.377953] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.377957] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.377961] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.377964] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.377979] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.377984] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.377989] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.377993] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.378019] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.378159] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.378186] [drm:dsi_cmds2buf_tx] ret=49 [ 2.378195] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.378205] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.378217] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.378240] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.378245] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.378249] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.378254] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.378258] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.378262] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.378267] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.378271] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.378275] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.378290] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.378295] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.378300] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.378304] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.378330] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.378470] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.378499] [drm:dsi_cmds2buf_tx] ret=50 [ 2.378507] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.378516] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.378528] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.378551] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.378556] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.378560] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.378564] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.378569] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.378573] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.378577] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.378581] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.378585] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.378600] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.378606] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.378610] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.378615] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.378640] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.378780] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.378807] [drm:dsi_cmds2buf_tx] ret=50 [ 2.378816] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.378825] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.378836] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.378859] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.378864] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.378869] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.378873] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.378878] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.378881] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.378885] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.378890] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.378893] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.378908] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.378914] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.378918] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.378923] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.378948] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.379088] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.379115] [drm:dsi_cmds2buf_tx] ret=50 [ 2.379124] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.379133] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.379145] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.379168] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.379173] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.379177] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.379181] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.379186] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.379190] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.379195] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.379199] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.379203] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.379218] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.379223] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.379227] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.379232] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.379257] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.379398] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.379426] [drm:dsi_cmds2buf_tx] ret=50 [ 2.379435] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.379444] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.379456] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.379479] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.379484] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.379488] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.379493] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.379498] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.379502] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.379506] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.379510] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.379514] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.379529] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.379535] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.379539] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.379544] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.379569] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.379709] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.379737] [drm:dsi_cmds2buf_tx] ret=50 [ 2.379746] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.379756] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.379767] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.379791] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.379796] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.379800] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.379804] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.379809] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.379813] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.379817] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.379821] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.379826] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.379841] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.379847] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.379851] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.379855] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.379881] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.380021] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.380049] [drm:dsi_cmds2buf_tx] ret=50 [ 2.380058] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.380068] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.380079] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.380103] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.380108] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.380112] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.380116] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.380121] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.380125] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.380130] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.380134] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.380138] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.380153] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.380158] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.380162] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.380167] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.380193] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.380333] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.380360] [drm:dsi_cmds2buf_tx] ret=50 [ 2.380369] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.380378] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.380390] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.380413] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.380418] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.380422] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.380426] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.380431] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.380435] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.380439] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.380443] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.380448] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.380463] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.380468] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.380473] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.380477] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.380503] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.380643] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.380670] [drm:dsi_cmds2buf_tx] ret=50 [ 2.380679] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.380688] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.380700] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.380723] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.380728] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.380733] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.380737] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.380742] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.380746] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.380750] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.380754] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.380758] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.380773] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.380779] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.380783] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.380788] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.380813] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.380953] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.380981] [drm:dsi_cmds2buf_tx] ret=50 [ 2.380990] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.380999] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.381011] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.381035] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.381040] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.381044] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.381048] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.381053] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.381058] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.381062] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.381066] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.381070] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.381085] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.381090] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.381095] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.381099] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.381125] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.381265] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.381292] [drm:dsi_cmds2buf_tx] ret=50 [ 2.381301] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.381310] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.381322] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.381346] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.381351] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.381355] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.381359] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.381364] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.381368] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.381372] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.381376] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.381380] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.381395] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.381400] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.381405] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.381409] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.381435] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.381575] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.381602] [drm:dsi_cmds2buf_tx] ret=50 [ 2.381611] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.381621] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.381633] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.381656] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.381661] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.381665] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.381670] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.381675] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.381679] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.381683] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.381687] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.381691] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.381706] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.381711] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.381716] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.381720] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.381746] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.381887] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.381915] [drm:dsi_cmds2buf_tx] ret=50 [ 2.381923] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.381933] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.381944] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.381967] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.381972] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.381976] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.381981] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.381986] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.381990] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.381994] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.381998] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.382002] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.382017] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.382022] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.382027] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.382031] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.382057] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.382198] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.382226] [drm:dsi_cmds2buf_tx] ret=49 [ 2.382235] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.382245] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.382256] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.382280] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.382285] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.382289] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.382293] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.382298] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.382302] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.382306] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.382310] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.382315] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.382330] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.382335] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.382339] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.382344] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.382369] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.382508] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.382663] [drm:dsi_cmds2buf_tx] ret=50 [ 2.382676] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.382690] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.382705] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.382735] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.382741] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.382746] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.382750] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.382755] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.382759] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.382764] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.382768] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.382772] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.382787] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.382793] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.382797] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.382801] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.382829] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.382971] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.383124] [drm:dsi_cmds2buf_tx] ret=50 [ 2.383136] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.383149] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.383164] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.383192] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.383198] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.383202] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.383207] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.383212] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.383216] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.383220] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.383224] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.383228] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.383243] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.383249] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.383254] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.383258] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.383286] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.383427] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.383580] [drm:dsi_cmds2buf_tx] ret=50 [ 2.383592] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.383605] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.383620] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.383648] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.383654] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.383659] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.383663] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.383668] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.383672] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.383676] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.383681] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.383685] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.383700] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.383705] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.383710] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.383714] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.383741] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.383881] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.384034] [drm:dsi_cmds2buf_tx] ret=50 [ 2.384046] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.384059] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.384073] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.384102] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.384108] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.384113] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.384117] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.384122] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.384126] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.384131] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.384134] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.384139] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.384154] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.384159] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.384164] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.384169] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.384196] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.384336] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.384488] [drm:dsi_cmds2buf_tx] ret=50 [ 2.384500] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.384513] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.384528] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.384557] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.384563] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.384568] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.384572] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.384577] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.384582] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.384586] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.384590] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.384594] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.384609] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.384615] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.384620] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.384624] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.384651] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.384791] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.384944] [drm:dsi_cmds2buf_tx] ret=50 [ 2.384956] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.384969] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.384984] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.385012] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.385018] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.385023] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.385027] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.385032] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.385036] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.385041] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.385045] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.385049] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.385064] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.385070] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.385075] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.385079] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.385106] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.385246] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.385400] [drm:dsi_cmds2buf_tx] ret=50 [ 2.385412] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.385426] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.385440] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.385468] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.385474] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.385479] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.385483] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.385488] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.385492] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.385497] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.385501] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.385505] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.385520] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.385526] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.385530] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.385535] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.385562] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.385715] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.385772] [drm:dsi_cmds2buf_tx] ret=50 [ 2.385781] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.385791] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.385804] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.385831] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.385836] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.385840] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.385844] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.385849] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.385853] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.385857] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.385861] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.385865] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.385880] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.385885] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.385889] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.385893] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.385919] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.386060] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.386088] [drm:dsi_cmds2buf_tx] ret=50 [ 2.386097] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.386108] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.386120] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.386144] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.386149] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.386154] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.386158] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.386163] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.386187] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.386192] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.386196] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.386201] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.386216] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.386221] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.386225] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.386230] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.386257] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.386399] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.386427] [drm:dsi_cmds2buf_tx] ret=50 [ 2.386435] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.386445] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.386457] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.386481] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.386485] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.386490] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.386494] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.386499] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.386503] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.386507] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.386511] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.386515] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.386530] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.386536] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.386540] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.386545] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.386571] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.386711] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.386739] [drm:dsi_cmds2buf_tx] ret=50 [ 2.386747] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.386756] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.386768] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.386792] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.386797] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.386801] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.386805] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.386810] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.386814] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.386818] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.386822] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.386827] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.386842] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.386847] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.386851] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.386856] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.386881] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.387021] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.387049] [drm:dsi_cmds2buf_tx] ret=50 [ 2.387058] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.387067] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.387079] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.387102] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.387107] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.387111] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.387115] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.387120] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.387124] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.387128] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.387132] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.387137] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.387151] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.387157] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.387161] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.387166] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.387191] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.387332] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.387359] [drm:dsi_cmds2buf_tx] ret=50 [ 2.387368] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.387377] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.387389] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.387413] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.387418] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.387422] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.387426] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.387431] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.387435] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.387438] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.387442] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.387446] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.387461] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.387466] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.387470] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.387474] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.387500] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.387640] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.387667] [drm:dsi_cmds2buf_tx] ret=50 [ 2.387676] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.387685] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.387697] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.387721] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.387725] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.387730] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.387734] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.387739] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.387742] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.387747] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.387751] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.387755] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.387770] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.387775] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.387780] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.387784] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.387810] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.387950] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.387978] [drm:dsi_cmds2buf_tx] ret=50 [ 2.387986] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.387996] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.388007] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.388030] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.388035] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.388039] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.388044] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.388048] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.388052] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.388056] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.388060] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.388065] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.388080] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.388085] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.388090] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.388094] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.388120] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.388260] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.388287] [drm:dsi_cmds2buf_tx] ret=50 [ 2.388296] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.388305] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.388317] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.388340] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.388345] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.388349] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.388354] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.388358] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.388362] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.388366] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.388371] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.388375] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.388390] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.388395] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.388400] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.388404] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.388430] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.388570] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.388597] [drm:dsi_cmds2buf_tx] ret=50 [ 2.388606] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.388616] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.388627] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.388650] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.388655] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.388659] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.388663] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.388668] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.388672] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.388676] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.388680] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.388685] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.388699] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.388705] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.388709] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.388713] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.388739] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.388879] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.388907] [drm:dsi_cmds2buf_tx] ret=50 [ 2.388915] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.388925] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.388936] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.388960] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.388965] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.388969] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.388974] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.388978] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.388982] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.388986] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.388991] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.388995] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.389010] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.389015] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.389020] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.389024] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.389050] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.389190] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.389218] [drm:dsi_cmds2buf_tx] ret=50 [ 2.389227] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.389236] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.389248] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.389272] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.389277] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.389281] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.389285] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.389289] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.389293] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.389297] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.389302] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.389306] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.389321] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.389326] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.389331] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.389335] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.389360] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.389501] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.389528] [drm:dsi_cmds2buf_tx] ret=50 [ 2.389537] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.389547] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.389558] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.389582] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.389587] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.389591] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.389595] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.389600] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.389604] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.389608] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.389612] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.389616] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.389631] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.389636] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.389641] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.389646] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.389671] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.389812] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.389839] [drm:dsi_cmds2buf_tx] ret=50 [ 2.389848] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.389857] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.389868] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.389891] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.389896] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.389901] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.389905] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.389910] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.389914] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.389918] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.389922] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.389926] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.389941] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.389947] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.389951] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.389955] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.389981] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.390121] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.390148] [drm:dsi_cmds2buf_tx] ret=50 [ 2.390157] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.390177] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.390189] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.390213] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.390217] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.390222] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.390226] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.390231] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.390235] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.390239] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.390243] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.390247] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.390262] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.390267] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.390272] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.390276] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.390302] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.390442] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.390470] [drm:dsi_cmds2buf_tx] ret=50 [ 2.390479] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.390488] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.390500] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.390523] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.390528] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.390532] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.390536] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.390542] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.390546] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.390550] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.390554] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.390558] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.390573] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.390578] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.390582] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.390587] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.390612] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.390753] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.390780] [drm:dsi_cmds2buf_tx] ret=50 [ 2.390789] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.390798] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.390810] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.390833] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.390839] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.390843] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.390847] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.390852] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.390856] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.390860] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.390864] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.390869] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.390884] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.390889] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.390894] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.390898] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.390924] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.391064] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.391092] [drm:dsi_cmds2buf_tx] ret=50 [ 2.391100] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.391110] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.391121] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.391145] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.391150] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.391154] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.391158] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.391163] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.391167] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.391172] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.391176] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.391180] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.391195] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.391200] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.391204] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.391209] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.391235] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.391375] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.391403] [drm:dsi_cmds2buf_tx] ret=50 [ 2.391411] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.391421] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.391432] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.391455] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.391460] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.391465] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.391469] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.391474] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.391478] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.391482] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.391486] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.391490] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.391505] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.391511] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.391515] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.391519] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.391545] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.391685] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.391713] [drm:dsi_cmds2buf_tx] ret=50 [ 2.391721] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.391730] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.391742] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.391765] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.391770] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.391774] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.391778] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.391783] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.391787] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.391791] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.391795] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.391799] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.391814] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.391819] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.391824] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.391828] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.391854] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.391994] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.392022] [drm:dsi_cmds2buf_tx] ret=50 [ 2.392031] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.392041] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.392052] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.392075] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.392080] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.392084] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.392088] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.392093] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.392097] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.392101] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.392105] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.392109] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.392124] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.392130] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.392134] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.392139] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.392164] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.392305] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.392333] [drm:dsi_cmds2buf_tx] ret=50 [ 2.392341] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.392351] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.392362] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.392386] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.392391] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.392395] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.392399] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.392404] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.392408] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.392412] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.392416] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.392420] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.392435] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.392441] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.392445] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.392449] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.392475] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.392615] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.392643] [drm:dsi_cmds2buf_tx] ret=50 [ 2.392651] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.392661] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.392673] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.392696] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.392701] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.392706] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.392710] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.392715] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.392719] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.392723] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.392727] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.392731] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.392746] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.392751] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.392756] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.392760] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.392786] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.392926] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.392954] [drm:dsi_cmds2buf_tx] ret=50 [ 2.392962] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.392972] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.392983] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.393006] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.393011] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.393015] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.393020] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.393024] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.393028] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.393033] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.393037] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.393041] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.393056] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.393061] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.393066] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.393070] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.393096] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.393236] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.393263] [drm:dsi_cmds2buf_tx] ret=50 [ 2.393272] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.393281] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.393293] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.393317] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.393322] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.393326] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.393330] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.393335] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.393339] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.393343] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.393347] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.393352] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.393367] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.393372] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.393376] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.393380] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.393406] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.393547] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.393575] [drm:dsi_cmds2buf_tx] ret=50 [ 2.393583] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.393592] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.393604] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.393627] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.393631] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.393635] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.393639] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.393644] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.393648] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.393653] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.393656] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.393661] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.393675] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.393681] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.393685] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.393689] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.393715] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.393855] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.393883] [drm:dsi_cmds2buf_tx] ret=50 [ 2.393892] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.393901] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.393913] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.393936] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.393941] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.393946] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.393950] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.393955] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.393959] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.393963] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.393967] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.393971] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.393986] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.393991] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.393996] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.394000] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.394026] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.394165] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.394192] [drm:dsi_cmds2buf_tx] ret=49 [ 2.394201] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.394211] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.394223] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.394247] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.394252] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.394257] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.394261] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.394265] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.394270] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.394273] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.394277] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.394281] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.394296] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.394301] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.394305] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.394309] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.394335] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.394474] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.394627] [drm:dsi_cmds2buf_tx] ret=50 [ 2.394640] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.394653] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.394668] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.394697] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.394703] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.394708] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.394712] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.394717] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.394721] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.394725] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.394729] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.394733] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.394749] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.394754] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.394759] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.394763] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.394791] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.394932] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.395085] [drm:dsi_cmds2buf_tx] ret=50 [ 2.395097] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.395110] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.395124] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.395153] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.395159] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.395164] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.395168] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.395173] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.395177] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.395181] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.395185] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.395190] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.395205] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.395211] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.395215] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.395220] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.395247] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.395399] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.395454] [drm:dsi_cmds2buf_tx] ret=50 [ 2.395464] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.395474] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.395487] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.395513] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.395518] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.395523] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.395527] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.395532] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.395536] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.395540] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.395545] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.395549] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.395564] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.395569] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.395574] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.395578] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.395605] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.395755] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.395810] [drm:dsi_cmds2buf_tx] ret=50 [ 2.395819] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.395829] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.395841] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.395867] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.395872] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.395876] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.395880] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.395885] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.395889] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.395893] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.395897] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.395902] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.395917] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.395922] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.395927] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.395931] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.395957] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.396107] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.396162] [drm:dsi_cmds2buf_tx] ret=50 [ 2.396171] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.396181] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.396193] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.396217] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.396223] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.396227] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.396231] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.396236] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.396240] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.396244] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.396248] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.396253] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.396268] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.396274] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.396278] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.396282] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.396308] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.396458] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.396513] [drm:dsi_cmds2buf_tx] ret=50 [ 2.396522] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.396532] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.396544] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.396568] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.396572] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.396577] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.396581] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.396586] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.396590] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.396594] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.396598] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.396602] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.396617] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.396623] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.396627] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.396631] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.396657] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.396809] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.396866] [drm:dsi_cmds2buf_tx] ret=50 [ 2.396875] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.396884] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.396896] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.396919] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.396924] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.396929] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.396933] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.396938] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.396942] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.396946] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.396950] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.396954] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.396969] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.396975] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.396980] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.396984] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.397010] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.397159] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.397215] [drm:dsi_cmds2buf_tx] ret=50 [ 2.397223] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.397233] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.397245] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.397269] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.397274] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.397278] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.397282] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.397287] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.397291] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.397295] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.397299] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.397304] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.397318] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.397324] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.397328] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.397333] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.397358] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.397499] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.397526] [drm:dsi_cmds2buf_tx] ret=50 [ 2.397535] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.397545] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.397556] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.397580] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.397584] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.397589] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.397593] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.397597] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.397601] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.397605] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.397609] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.397613] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.397628] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.397634] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.397638] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.397643] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.397668] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.397808] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.397835] [drm:dsi_cmds2buf_tx] ret=50 [ 2.397844] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.397853] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.397865] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.397888] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.397893] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.397897] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.397902] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.397906] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.397910] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.397914] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.397918] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.397922] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.397938] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.397943] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.397948] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.397952] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.397977] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.398118] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.398145] [drm:dsi_cmds2buf_tx] ret=50 [ 2.398154] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.398164] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.398194] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.398219] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.398224] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.398228] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.398232] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.398236] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.398240] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.398245] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.398249] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.398253] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.398267] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.398272] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.398276] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.398280] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.398304] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.398326] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.398354] [drm:dsi_cmds2buf_tx] ret=50 [ 2.398363] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.398373] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.398384] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.398408] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.398412] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.398416] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.398421] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.398426] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.398430] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.398434] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.398438] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.398442] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.398457] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.398463] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.398467] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.398471] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.398497] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.398637] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.398665] [drm:dsi_cmds2buf_tx] ret=50 [ 2.398673] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.398683] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.398694] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.398718] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.398723] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.398727] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.398732] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.398737] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.398741] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.398745] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.398749] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.398753] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.398768] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.398774] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.398778] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.398782] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.398808] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.398948] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.398975] [drm:dsi_cmds2buf_tx] ret=50 [ 2.398984] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.398993] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.399005] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.399028] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.399033] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.399037] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.399041] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.399046] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.399050] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.399054] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.399058] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.399063] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.399077] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.399083] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.399087] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.399091] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.399117] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.399257] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.399285] [drm:dsi_cmds2buf_tx] ret=50 [ 2.399293] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.399303] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.399314] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.399337] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.399342] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.399346] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.399351] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.399356] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.399360] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.399364] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.399368] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.399372] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.399387] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.399393] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.399397] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.399402] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.399427] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.399567] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.399595] [drm:dsi_cmds2buf_tx] ret=50 [ 2.399604] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.399613] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.399625] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.399648] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.399653] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.399657] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.399662] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.399666] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.399670] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.399675] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.399679] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.399683] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.399698] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.399704] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.399708] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.399712] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.399738] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.399878] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.399906] [drm:dsi_cmds2buf_tx] ret=50 [ 2.399915] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.399924] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.399936] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.399959] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.399964] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.399969] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.399973] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.399978] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.399982] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.399986] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.399990] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.399994] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.400009] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.400015] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.400019] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.400024] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.400050] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.400190] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.400217] [drm:dsi_cmds2buf_tx] ret=50 [ 2.400226] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.400235] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.400247] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.400270] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.400275] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.400279] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.400284] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.400288] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.400292] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.400296] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.400300] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.400305] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.400320] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.400325] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.400330] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.400334] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.400360] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.400500] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.400527] [drm:dsi_cmds2buf_tx] ret=50 [ 2.400536] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.400545] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.400557] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.400580] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.400585] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.400589] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.400593] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.400598] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.400602] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.400606] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.400610] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.400614] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.400629] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.400635] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.400639] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.400643] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.400669] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.400809] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.400836] [drm:dsi_cmds2buf_tx] ret=50 [ 2.400845] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.400854] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.400866] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.400889] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.400894] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.400898] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.400902] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.400907] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.400911] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.400915] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.400919] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.400924] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.400938] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.400944] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.400948] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.400953] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.400978] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.401118] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.401146] [drm:dsi_cmds2buf_tx] ret=50 [ 2.401155] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.401164] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.401176] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.401199] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.401205] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.401209] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.401213] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.401218] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.401222] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.401226] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.401230] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.401234] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.401249] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.401254] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.401259] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.401263] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.401288] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.401428] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.401455] [drm:dsi_cmds2buf_tx] ret=50 [ 2.401464] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.401474] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.401485] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.401509] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.401514] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.401518] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.401522] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.401527] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.401531] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.401535] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.401539] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.401543] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.401558] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.401563] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.401568] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.401572] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.401598] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.401738] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.401766] [drm:dsi_cmds2buf_tx] ret=50 [ 2.401775] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.401784] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.401796] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.401819] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.401824] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.401828] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.401833] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.401837] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.401841] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.401845] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.401850] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.401854] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.401869] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.401874] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.401879] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.401883] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.401909] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.402049] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.402077] [drm:dsi_cmds2buf_tx] ret=50 [ 2.402085] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.402095] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.402106] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.402130] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.402135] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.402139] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.402143] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.402147] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.402151] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.402155] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.402160] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.402164] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.402197] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.402203] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.402208] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.402212] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.402239] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.402386] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.402414] [drm:dsi_cmds2buf_tx] ret=50 [ 2.402423] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.402432] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.402444] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.402468] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.402472] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.402476] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.402480] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.402485] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.402490] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.402494] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.402498] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.402502] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.402517] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.402522] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.402527] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.402531] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.402557] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.402697] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.402725] [drm:dsi_cmds2buf_tx] ret=50 [ 2.402733] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.402743] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.402754] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.402777] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.402782] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.402786] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.402790] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.402795] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.402799] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.402803] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.402807] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.402811] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.402826] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.402832] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.402836] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.402841] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.402866] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.403006] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.403034] [drm:dsi_cmds2buf_tx] ret=50 [ 2.403043] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.403052] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.403064] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.403087] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.403092] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.403096] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.403101] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.403105] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.403109] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.403113] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.403117] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.403121] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.403135] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.403140] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.403144] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.403148] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.403174] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.403315] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.403342] [drm:dsi_cmds2buf_tx] ret=50 [ 2.403351] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.403360] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.403372] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.403395] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.403400] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.403404] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.403408] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.403413] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.403417] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.403421] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.403425] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.403430] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.403444] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.403450] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.403455] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.403459] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.403485] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.403625] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.403652] [drm:dsi_cmds2buf_tx] ret=50 [ 2.403661] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.403670] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.403682] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.403705] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.403710] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.403715] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.403719] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.403724] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.403728] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.403732] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.403736] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.403740] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.403755] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.403760] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.403765] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.403769] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.403795] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.403935] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.403962] [drm:dsi_cmds2buf_tx] ret=50 [ 2.403971] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.403981] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.403992] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.404016] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.404020] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.404025] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.404029] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.404034] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.404038] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.404042] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.404046] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.404051] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.404066] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.404071] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.404075] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.404080] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.404105] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.404246] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.404273] [drm:dsi_cmds2buf_tx] ret=50 [ 2.404282] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.404291] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.404303] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.404326] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.404331] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.404335] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.404339] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.404344] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.404348] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.404353] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.404357] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.404361] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.404376] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.404382] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.404386] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.404390] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.404416] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.404556] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.404583] [drm:dsi_cmds2buf_tx] ret=50 [ 2.404592] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.404602] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.404613] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.404637] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.404641] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.404646] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.404650] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.404655] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.404659] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.404663] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.404667] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.404671] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.404686] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.404692] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.404696] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.404700] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.404726] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.404866] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.404894] [drm:dsi_cmds2buf_tx] ret=50 [ 2.404902] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.404912] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.404924] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.404946] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.404951] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.404956] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.404960] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.404965] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.404969] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.404973] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.404977] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.404981] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.404996] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.405002] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.405006] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.405011] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.405037] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.405177] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.405205] [drm:dsi_cmds2buf_tx] ret=50 [ 2.405214] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.405224] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.405235] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.405259] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.405264] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.405268] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.405272] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.405277] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.405281] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.405285] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.405289] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.405293] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.405308] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.405314] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.405318] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.405322] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.405347] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.405487] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.405515] [drm:dsi_cmds2buf_tx] ret=50 [ 2.405523] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.405533] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.405545] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.405568] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.405572] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.405577] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.405581] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.405586] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.405590] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.405594] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.405598] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.405602] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.405617] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.405623] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.405627] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.405631] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.405657] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.405797] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.405825] [drm:dsi_cmds2buf_tx] ret=50 [ 2.405834] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.405843] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.405854] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.405878] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.405883] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.405887] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.405891] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.405896] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.405900] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.405904] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.405908] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.405912] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.405927] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.405932] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.405937] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.405942] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.405967] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.406107] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.406135] [drm:dsi_cmds2buf_tx] ret=50 [ 2.406143] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.406153] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.406175] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.406200] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.406206] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.406210] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.406214] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.406218] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.406222] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.406226] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.406230] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.406234] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.406248] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.406253] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.406257] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.406261] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.406286] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.406316] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.406344] [drm:dsi_cmds2buf_tx] ret=50 [ 2.406353] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.406363] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.406375] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.406399] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.406403] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.406408] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.406412] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.406416] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.406421] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.406425] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.406429] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.406433] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.406448] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.406454] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.406458] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.406462] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.406488] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.406627] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.406779] [drm:dsi_cmds2buf_tx] ret=50 [ 2.406792] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.406805] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.406820] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.406849] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.406855] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.406860] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.406865] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.406870] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.406874] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.406878] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.406882] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.406886] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.406902] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.406907] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.406912] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.406916] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.406943] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.407083] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.407236] [drm:dsi_cmds2buf_tx] ret=50 [ 2.407248] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.407261] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.407276] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.407304] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.407310] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.407315] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.407319] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.407324] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.407328] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.407333] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.407337] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.407342] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.407357] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.407362] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.407367] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.407371] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.407399] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.407539] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.407691] [drm:dsi_cmds2buf_tx] ret=50 [ 2.407704] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.407717] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.407731] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.407760] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.407766] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.407771] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.407775] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.407780] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.407784] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.407788] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.407792] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.407796] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.407812] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.407817] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.407822] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.407826] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.407854] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.407995] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.408148] [drm:dsi_cmds2buf_tx] ret=50 [ 2.408160] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.408174] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.408188] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.408217] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.408223] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.408228] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.408233] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.408237] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.408242] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.408246] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.408250] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.408254] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.408270] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.408275] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.408280] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.408284] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.408312] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.408452] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.408605] [drm:dsi_cmds2buf_tx] ret=50 [ 2.408618] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.408631] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.408646] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.408674] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.408680] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.408685] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.408689] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.408694] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.408698] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.408703] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.408707] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.408712] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.408727] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.408732] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.408737] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.408741] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.408769] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.408910] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.409063] [drm:dsi_cmds2buf_tx] ret=50 [ 2.409075] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.409088] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.409102] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.409130] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.409136] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.409141] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.409146] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.409151] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.409155] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.409159] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.409164] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.409168] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.409183] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.409189] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.409193] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.409198] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.409225] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.409364] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.409515] [drm:dsi_cmds2buf_tx] ret=50 [ 2.409527] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.409540] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.409555] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.409583] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.409589] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.409594] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.409598] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.409603] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.409607] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.409612] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.409616] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.409620] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.409636] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.409641] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.409646] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.409650] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.409678] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.409830] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.409887] [drm:dsi_cmds2buf_tx] ret=50 [ 2.409897] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.409907] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.409920] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.409946] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.409951] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.409955] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.409960] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.409964] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.409968] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.409973] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.409977] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.409981] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.409996] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.410001] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.410006] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.410010] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.410037] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.410177] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.410205] [drm:dsi_cmds2buf_tx] ret=49 [ 2.410215] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.410225] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.410237] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.410262] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.410267] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.410271] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.410275] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.410279] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.410283] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.410287] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.410291] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.410294] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.410310] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.410315] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.410320] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.410324] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.410350] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.410491] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.410646] [drm:dsi_cmds2buf_tx] ret=50 [ 2.410659] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.410672] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.410686] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.410715] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.410721] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.410726] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.410730] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.410735] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.410739] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.410743] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.410748] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.410752] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.410767] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.410773] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.410777] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.410781] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.410809] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.410948] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.411104] [drm:dsi_cmds2buf_tx] ret=50 [ 2.411116] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.411129] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.411144] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.411172] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.411178] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.411183] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.411188] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.411193] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.411197] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.411201] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.411205] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.411209] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.411224] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.411230] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.411234] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.411239] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.411266] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.411407] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.411562] [drm:dsi_cmds2buf_tx] ret=50 [ 2.411575] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.411588] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.411602] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.411630] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.411637] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.411642] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.411646] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.411651] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.411655] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.411659] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.411663] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.411667] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.411683] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.411689] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.411693] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.411697] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.411724] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.411865] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.412018] [drm:dsi_cmds2buf_tx] ret=50 [ 2.412030] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.412044] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.412059] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.412087] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.412093] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.412098] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.412102] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.412107] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.412111] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.412116] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.412120] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.412124] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.412139] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.412145] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.412149] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.412153] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.412181] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.412321] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.412474] [drm:dsi_cmds2buf_tx] ret=50 [ 2.412487] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.412500] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.412514] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.412543] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.412549] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.412554] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.412558] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.412564] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.412568] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.412572] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.412576] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.412580] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.412595] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.412601] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.412606] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.412610] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.412638] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.412778] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.412931] [drm:dsi_cmds2buf_tx] ret=50 [ 2.412943] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.412956] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.412970] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.412999] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.413006] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.413010] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.413015] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.413020] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.413024] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.413028] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.413033] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.413037] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.413052] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.413058] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.413062] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.413066] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.413094] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.413234] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.413388] [drm:dsi_cmds2buf_tx] ret=50 [ 2.413401] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.413414] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.413428] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.413456] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.413462] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.413467] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.413472] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.413477] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.413481] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.413485] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.413489] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.413494] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.413509] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.413514] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.413519] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.413523] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.413551] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.413704] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.413761] [drm:dsi_cmds2buf_tx] ret=50 [ 2.413770] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.413780] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.413793] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.413819] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.413824] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.413828] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.413832] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.413837] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.413841] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.413845] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.413849] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.413853] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.413868] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.413874] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.413878] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.413882] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.413909] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.414049] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.414077] [drm:dsi_cmds2buf_tx] ret=50 [ 2.414086] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.414096] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.414108] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.414133] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.414138] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.414142] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.414147] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.414151] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.414155] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.414160] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.414164] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.414186] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.414201] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.414207] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.414211] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.414215] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.414241] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.414311] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.414339] [drm:dsi_cmds2buf_tx] ret=50 [ 2.414347] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.414357] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.414369] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.414392] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.414397] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.414402] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.414406] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.414411] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.414415] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.414419] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.414423] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.414428] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.414443] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.414448] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.414452] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.414457] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.414483] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.414622] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.414773] [drm:dsi_cmds2buf_tx] ret=50 [ 2.414786] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.414798] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.414813] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.414841] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.414847] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.414852] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.414856] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.414861] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.414866] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.414870] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.414874] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.414878] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.414894] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.414900] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.414904] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.414908] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.414936] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.415075] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.415226] [drm:dsi_cmds2buf_tx] ret=50 [ 2.415239] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.415252] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.415267] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.415295] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.415301] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.415305] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.415310] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.415315] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.415319] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.415323] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.415328] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.415332] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.415347] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.415353] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.415357] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.415361] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.415389] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.415529] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.415681] [drm:dsi_cmds2buf_tx] ret=50 [ 2.415694] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.415707] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.415721] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.415749] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.415755] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.415760] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.415764] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.415769] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.415773] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.415778] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.415782] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.415786] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.415801] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.415807] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.415811] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.415816] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.415843] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.415983] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.416134] [drm:dsi_cmds2buf_tx] ret=50 [ 2.416146] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.416159] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.416174] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.416203] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.416209] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.416213] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.416218] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.416223] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.416227] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.416231] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.416235] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.416240] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.416255] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.416261] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.416265] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.416269] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.416296] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.416435] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.416586] [drm:dsi_cmds2buf_tx] ret=50 [ 2.416599] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.416612] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.416627] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.416655] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.416661] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.416666] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.416670] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.416675] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.416679] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.416684] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.416688] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.416692] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.416707] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.416713] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.416717] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.416721] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.416749] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.416902] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.416958] [drm:dsi_cmds2buf_tx] ret=50 [ 2.416967] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.416978] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.416991] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.417017] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.417022] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.417027] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.417031] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.417035] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.417040] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.417044] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.417048] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.417052] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.417067] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.417073] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.417078] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.417082] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.417109] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.417260] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.417316] [drm:dsi_cmds2buf_tx] ret=50 [ 2.417325] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.417335] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.417348] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.417373] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.417378] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.417382] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.417386] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.417391] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.417395] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.417399] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.417404] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.417408] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.417423] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.417428] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.417433] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.417437] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.417463] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.417614] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.417670] [drm:dsi_cmds2buf_tx] ret=50 [ 2.417679] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.417690] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.417702] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.417726] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.417731] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.417736] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.417740] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.417745] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.417749] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.417753] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.417757] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.417761] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.417776] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.417781] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.417785] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.417790] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.417816] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.417957] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.417985] [drm:dsi_cmds2buf_tx] ret=50 [ 2.417993] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.418003] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.418015] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.418039] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.418044] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.418048] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.418053] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.418057] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.418061] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.418066] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.418070] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.418074] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.418089] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.418095] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.418099] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.418103] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.418129] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.418273] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.418302] [drm:dsi_cmds2buf_tx] ret=49 [ 2.418311] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.418322] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.418334] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.418358] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.418363] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.418367] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.418371] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.418376] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.418380] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.418385] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.418389] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.418393] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.418408] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.418414] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.418418] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.418422] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.418448] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.418588] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.418616] [drm:dsi_cmds2buf_tx] ret=50 [ 2.418625] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.418635] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.418646] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.418669] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.418674] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.418679] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.418683] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.418688] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.418692] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.418696] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.418700] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.418704] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.418719] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.418725] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.418729] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.418733] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.418759] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.418900] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.419056] [drm:dsi_cmds2buf_tx] ret=50 [ 2.419069] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.419081] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.419096] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.419124] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.419131] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.419135] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.419140] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.419144] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.419148] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.419153] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.419157] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.419161] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.419176] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.419182] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.419186] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.419190] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.419218] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.419359] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.419514] [drm:dsi_cmds2buf_tx] ret=50 [ 2.419526] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.419539] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.419554] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.419582] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.419588] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.419592] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.419597] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.419602] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.419606] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.419611] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.419615] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.419619] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.419634] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.419640] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.419644] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.419649] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.419676] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.419817] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.419846] [drm:dsi_cmds2buf_tx] ret=50 [ 2.419855] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.419865] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.419878] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.419903] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.419908] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.419913] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.419917] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.419922] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.419926] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.419931] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.419935] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.419939] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.419954] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.419960] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.419964] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.419968] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.419995] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.420135] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.420164] [drm:dsi_cmds2buf_tx] ret=50 [ 2.420173] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.420183] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.420195] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.420219] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.420224] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.420229] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.420233] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.420237] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.420241] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.420246] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.420250] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.420254] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.420269] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.420275] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.420279] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.420283] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.420310] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.420450] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.420478] [drm:dsi_cmds2buf_tx] ret=50 [ 2.420487] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.420496] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.420508] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.420532] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.420537] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.420541] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.420545] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.420550] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.420554] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.420559] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.420563] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.420567] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.420582] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.420587] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.420591] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.420596] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.420622] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.420763] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.420791] [drm:dsi_cmds2buf_tx] ret=50 [ 2.420799] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.420808] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.420820] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.420844] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.420849] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.420853] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.420858] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.420862] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.420866] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.420870] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.420874] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.420879] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.420894] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.420899] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.420903] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.420908] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.420933] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.421074] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.421102] [drm:dsi_cmds2buf_tx] ret=50 [ 2.421110] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.421121] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.421132] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.421155] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.421160] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.421164] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.421169] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.421173] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.421177] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.421182] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.421186] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.421190] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.421205] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.421210] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.421215] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.421219] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.421244] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.421384] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.421412] [drm:dsi_cmds2buf_tx] ret=50 [ 2.421421] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.421431] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.421442] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.421466] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.421471] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.421475] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.421479] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.421484] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.421488] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.421492] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.421496] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.421501] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.421515] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.421521] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.421525] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.421530] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.421555] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.421695] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.421723] [drm:dsi_cmds2buf_tx] ret=50 [ 2.421731] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.421741] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.421753] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.421776] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.421781] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.421785] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.421790] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.421794] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.421798] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.421802] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.421807] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.421811] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.421826] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.421831] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.421836] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.421840] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.421866] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.422006] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.422033] [drm:dsi_cmds2buf_tx] ret=50 [ 2.422042] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.422052] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.422063] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.422087] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.422092] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.422096] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.422100] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.422105] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.422109] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.422113] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.422117] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.422121] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.422136] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.422142] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.422146] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.422150] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.422187] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.422305] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.422333] [drm:dsi_cmds2buf_tx] ret=50 [ 2.422342] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.422352] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.422363] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.422387] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.422392] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.422396] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.422400] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.422405] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.422409] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.422413] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.422417] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.422421] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.422437] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.422442] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.422447] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.422451] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.422477] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.422617] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.422644] [drm:dsi_cmds2buf_tx] ret=50 [ 2.422653] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.422663] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.422674] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.422698] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.422702] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.422706] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.422711] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.422715] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.422719] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.422723] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.422728] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.422732] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.422747] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.422752] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.422756] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.422760] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.422786] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.422926] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.422954] [drm:dsi_cmds2buf_tx] ret=50 [ 2.422962] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.422972] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.422984] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.423007] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.423012] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.423016] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.423020] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.423025] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.423028] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.423032] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.423036] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.423040] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.423054] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.423059] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.423064] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.423068] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.423094] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.423234] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.423262] [drm:dsi_cmds2buf_tx] ret=50 [ 2.423270] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.423280] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.423292] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.423315] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.423320] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.423324] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.423329] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.423333] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.423337] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.423342] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.423346] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.423350] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.423365] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.423370] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.423375] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.423379] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.423405] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.423545] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.423572] [drm:dsi_cmds2buf_tx] ret=50 [ 2.423581] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.423591] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.423603] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.423626] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.423631] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.423635] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.423639] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.423644] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.423648] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.423652] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.423656] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.423660] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.423675] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.423681] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.423685] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.423689] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.423715] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.423855] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.423883] [drm:dsi_cmds2buf_tx] ret=50 [ 2.423892] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.423902] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.423913] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.423936] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.423941] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.423945] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.423950] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.423955] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.423959] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.423963] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.423967] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.423971] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.423986] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.423991] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.423996] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.424000] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.424026] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.424166] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.424194] [drm:dsi_cmds2buf_tx] ret=50 [ 2.424202] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.424212] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.424223] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.424246] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.424251] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.424256] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.424260] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.424265] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.424269] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.424273] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.424277] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.424281] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.424296] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.424302] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.424306] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.424310] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.424336] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.424476] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.424504] [drm:dsi_cmds2buf_tx] ret=50 [ 2.424512] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.424522] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.424534] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.424557] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.424562] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.424566] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.424570] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.424575] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.424579] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.424584] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.424588] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.424592] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.424607] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.424612] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.424616] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.424621] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.424647] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.424787] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.424814] [drm:dsi_cmds2buf_tx] ret=50 [ 2.424823] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.424833] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.424844] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.424868] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.424872] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.424877] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.424881] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.424886] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.424890] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.424894] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.424898] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.424902] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.424917] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.424923] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.424927] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.424931] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.424957] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.425097] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.425125] [drm:dsi_cmds2buf_tx] ret=50 [ 2.425133] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.425143] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.425155] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.425178] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.425183] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.425187] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.425191] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.425196] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.425200] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.425204] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.425209] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.425213] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.425228] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.425233] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.425237] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.425242] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.425268] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.425408] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.425436] [drm:dsi_cmds2buf_tx] ret=50 [ 2.425445] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.425455] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.425466] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.425489] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.425494] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.425499] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.425503] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.425508] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.425512] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.425516] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.425520] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.425525] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.425539] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.425545] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.425549] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.425553] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.425579] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.425720] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.425747] [drm:dsi_cmds2buf_tx] ret=50 [ 2.425756] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.425765] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.425777] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.425800] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.425805] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.425809] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.425813] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.425818] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.425822] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.425826] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.425830] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.425834] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.425849] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.425855] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.425859] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.425863] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.425889] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.426029] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.426056] [drm:dsi_cmds2buf_tx] ret=50 [ 2.426065] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.426075] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.426086] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.426109] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.426114] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.426119] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.426123] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.426127] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.426132] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.426136] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.426140] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.426144] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.426159] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.426175] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.426180] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.426185] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.426211] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.426352] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.426380] [drm:dsi_cmds2buf_tx] ret=50 [ 2.426389] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.426399] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.426410] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.426434] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.426439] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.426443] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.426447] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.426452] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.426456] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.426460] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.426464] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.426469] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.426483] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.426489] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.426493] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.426498] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.426524] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.426664] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.426691] [drm:dsi_cmds2buf_tx] ret=50 [ 2.426700] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.426710] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.426721] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.426745] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.426750] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.426754] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.426758] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.426763] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.426767] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.426771] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.426775] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.426780] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.426795] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.426800] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.426804] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.426809] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.426834] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.426974] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.427002] [drm:dsi_cmds2buf_tx] ret=50 [ 2.427011] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.427020] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.427032] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.427055] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.427060] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.427065] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.427069] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.427073] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.427078] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.427082] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.427086] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.427090] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.427105] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.427111] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.427115] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.427119] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.427145] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.427285] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.427313] [drm:dsi_cmds2buf_tx] ret=50 [ 2.427322] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.427332] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.427343] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.427366] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.427371] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.427375] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.427379] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.427384] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.427388] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.427392] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.427397] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.427401] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.427415] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.427421] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.427426] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.427430] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.427455] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.427595] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.427623] [drm:dsi_cmds2buf_tx] ret=50 [ 2.427631] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.427641] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.427652] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.427675] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.427680] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.427683] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.427687] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.427692] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.427696] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.427700] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.427704] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.427708] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.427723] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.427729] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.427733] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.427737] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.427763] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.427903] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.427930] [drm:dsi_cmds2buf_tx] ret=50 [ 2.427938] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.427948] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.427960] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.427983] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.427988] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.427992] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.427996] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.428001] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.428005] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.428009] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.428013] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.428017] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.428032] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.428037] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.428042] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.428046] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.428072] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.428212] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.428240] [drm:dsi_cmds2buf_tx] ret=50 [ 2.428248] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.428258] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.428270] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.428293] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.428298] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.428303] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.428307] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.428312] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.428316] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.428320] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.428324] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.428328] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.428343] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.428349] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.428353] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.428357] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.428383] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.428522] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.428550] [drm:dsi_cmds2buf_tx] ret=50 [ 2.428559] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.428568] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.428580] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.428603] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.428608] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.428613] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.428617] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.428622] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.428626] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.428630] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.428634] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.428638] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.428653] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.428659] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.428663] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.428667] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.428693] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.428833] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.428861] [drm:dsi_cmds2buf_tx] ret=50 [ 2.428869] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.428879] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.428890] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.428913] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.428918] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.428923] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.428927] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.428932] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.428936] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.428940] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.428944] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.428948] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.428963] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.428969] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.428973] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.428978] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.429003] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.429144] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.429171] [drm:dsi_cmds2buf_tx] ret=50 [ 2.429180] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.429189] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.429201] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.429224] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.429229] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.429233] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.429238] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.429242] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.429247] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.429251] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.429255] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.429259] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.429274] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.429279] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.429284] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.429288] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.429314] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.429454] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.429481] [drm:dsi_cmds2buf_tx] ret=50 [ 2.429490] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.429500] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.429511] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.429535] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.429539] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.429544] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.429548] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.429553] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.429557] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.429561] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.429565] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.429570] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.429584] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.429590] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.429594] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.429598] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.429624] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.429764] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.429792] [drm:dsi_cmds2buf_tx] ret=50 [ 2.429801] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.429811] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.429822] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.429846] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.429850] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.429855] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.429859] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.429864] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.429868] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.429872] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.429876] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.429880] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.429895] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.429900] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.429905] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.429909] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.429935] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.430075] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.430102] [drm:dsi_cmds2buf_tx] ret=50 [ 2.430111] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.430121] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.430132] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.430156] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.430161] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.430175] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.430180] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.430184] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.430188] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.430192] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.430197] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.430201] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.430216] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.430221] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.430226] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.430230] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.430256] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.430398] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.430426] [drm:dsi_cmds2buf_tx] ret=50 [ 2.430434] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.430444] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.430456] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.430480] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.430484] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.430488] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.430492] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.430497] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.430501] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.430506] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.430510] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.430514] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.430529] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.430534] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.430538] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.430543] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.430569] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.430709] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.430736] [drm:dsi_cmds2buf_tx] ret=50 [ 2.430745] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.558332] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=133627, byteclk=100220250 [ 2.558351] msm_dsi 1a94000.dsi: _set_opp: switching OPP: Freq 125000000 -> 125000000 Hz, Level 128 -> 128, Bw 0 -> 0 [ 2.558380] [drm:dsi_pll_28nm_clk_set_rate] refclk_cfg = 1 [ 2.558386] [drm:dsi_pll_28nm_clk_set_rate] div_fb = 10439 [ 2.558392] [drm:dsi_pll_28nm_clk_set_rate] frac_n_value = 28770 [ 2.558396] [drm:dsi_pll_28nm_clk_set_rate] Generated VCO Clock: 400857600 [ 2.558401] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg0=0 [ 2.558405] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg1=73 [ 2.558409] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg2=98 [ 2.558413] [drm:dsi_pll_28nm_clk_set_rate] sdm_cfg3=112 [ 2.558417] [drm:dsi_pll_28nm_clk_set_rate] cal_cfg10=144, cal_cfg11=1 [ 2.558433] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_dc_off = 9 [ 2.558439] [drm:dsi_pll_28nm_clk_recalc_rate] sdm_freq_seed = 28770 [ 2.558443] [drm:dsi_pll_28nm_clk_recalc_rate] vco rate = 400857421 [ 2.558447] [drm:dsi_pll_28nm_clk_recalc_rate] returning vco rate = 400857421 [ 2.558475] [drm:dsi_intr_ctrl] intr=a220aa02 enable=1 [ 2.558619] [drm:dsi_host_irq] isr=0xa220aa03, id=0 [ 2.558775] [drm:dsi_cmds2buf_tx] ret=50 [ 2.558788] [drm:dsi_intr_ctrl] intr=a220aa00 enable=0 [ 2.558821] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0 [ 2.558830] [drm:dpu_get_dpu_format_ext] fmt RG24 mod 0x0 ubwc 0 yuv 0 [ 2.558839] [drm:dpu_encoder_phys_vid_enable] enc31 intf1 [ 2.558847] [drm:dpu_reg_write] *ERROR* [SSPP_SPARE:0x28] <= 0x0 [ 2.558857] [drm:dpu_reg_write] *ERROR* [SPLIT_DISPLAY_LOWER_PIPE_CTRL:0x3F0] <= 0x0 [ 2.558866] [drm:dpu_reg_write] *ERROR* [SPLIT_DISPLAY_UPPER_PIPE_CTRL:0x2F8] <= 0x0 [ 2.558874] [drm:dpu_reg_write] *ERROR* [SPLIT_DISPLAY_EN:0x2F4] <= 0x0 [ 2.558882] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 enabling mode: [ 2.558890] [drm:drm_mode_debug_printmodeline] Modeline "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 2.558917] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0 [ 2.558923] [drm:dpu_get_dpu_format_ext] fmt RG24 mod 0x0 ubwc 0 yuv 0 [ 2.558930] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 fmt_fourcc 0x34324752 [ 2.558939] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x4] [ 2.558947] [drm:dpu_reg_write] *ERROR* [INTF_HSYNC_CTL:0x8] <= 0x47C0008 [ 2.558956] [drm:dpu_reg_write] *ERROR* [INTF_VSYNC_PERIOD_F0:0xC] <= 0x21FBB0 [ 2.558964] [drm:dpu_reg_write] *ERROR* [INTF_VSYNC_PULSE_WIDTH_F0:0x14] <= 0x8F8 [ 2.558973] [drm:dpu_reg_write] *ERROR* [INTF_DISPLAY_HCTL:0x3C] <= 0x453001C [ 2.558981] [drm:dpu_reg_write] *ERROR* [INTF_DISPLAY_V_START_F0:0x1C] <= 0x35D0 [ 2.558989] [drm:dpu_reg_write] *ERROR* [INTF_DISPLAY_V_END_F0:0x24] <= 0x21D7CF [ 2.558997] [drm:dpu_reg_write] *ERROR* [INTF_ACTIVE_HCTL:0x40] <= 0x0 [ 2.559005] [drm:dpu_reg_write] *ERROR* [INTF_ACTIVE_V_START_F0:0x2C] <= 0x0 [ 2.559012] [drm:dpu_reg_write] *ERROR* [INTF_ACTIVE_V_END_F0:0x34] <= 0x0 [ 2.559020] [drm:dpu_reg_write] *ERROR* [INTF_BORDER_COLOR:0x44] <= 0x0 [ 2.559027] [drm:dpu_reg_write] *ERROR* [INTF_UNDERFLOW_COLOR:0x48] <= 0xFF [ 2.559035] [drm:dpu_reg_write] *ERROR* [INTF_HSYNC_SKEW:0x4C] <= 0x0 [ 2.559043] [drm:dpu_reg_write] *ERROR* [INTF_POLARITY_CTL:0x50] <= 0x0 [ 2.559050] [drm:dpu_reg_write] *ERROR* [INTF_FRAME_LINE_COUNT_EN:0xA8] <= 0x3 [ 2.559058] [drm:dpu_reg_write] *ERROR* [INTF_CONFIG:0x4] <= 0x40000 [ 2.559065] [drm:dpu_reg_write] *ERROR* [INTF_PANEL_FORMAT:0x90] <= 0x213F [ 2.559074] [drm:dpu_reg_write] *ERROR* [CTL_TOP:0x14] <= 0x20 [ 2.559084] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 room in vfp for needed prefetch [ 2.559090] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 v_front_porch 8 v_back_porch 10 vsync_pulse_width 2 [ 2.559099] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 wc_lines 14 needed_vfp_lines 2 actual_vfp_lines 2 [ 2.559107] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 vfp_fetch_lines 2 vfp_fetch_start_vsync_counter 2224825 [ 2.559115] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x4] [ 2.559122] [drm:dpu_reg_write] *ERROR* [INTF_PROG_FETCH_START:0x170] <= 0x21F2B9 [ 2.559131] [drm:dpu_reg_write] *ERROR* [INTF_CONFIG:0x4] <= 0x80040000 [ 2.559140] [drm:dpu_encoder_phys_vid_enable] enc31 intf1 update pending flush ctl 0 intf 2 [ 2.559149] [drm:_dpu_encoder_irq_enable] enc31 [ 2.559155] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=1/0 [ 2.559163] [drm:dpu_reg_write] *ERROR* [reg->clr_off:0x18] <= 0x8000000 [ 2.559172] [drm:dpu_reg_write] *ERROR* [reg->en_off:0x10] <= 0x8000000 [ 2.559181] [drm:dpu_reg_write] *ERROR* [reg->clr_off:0x18] <= 0x4000000 [ 2.559189] [drm:dpu_reg_write] *ERROR* [reg->en_off:0x10] <= 0xC000000 [ 2.559271] msm_dpu 1a01000.display-controller: [drm:msm_crtc_enable_vblank] crtc=63 [ 2.559287] msm_dpu 1a01000.display-controller: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0 [ 2.559303] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.559313] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-13)@ 2.553147 -> 2.553258 [e 8 us, 0 rep] [ 2.559329] msm_dpu 1a01000.display-controller: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=1, diff=0, hw=0 hw_last=0 [ 2.559341] DPU:KMS: dpu_kms_flush_commit [ 2.559344] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.559352] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 2.559359] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 2.559364] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 2.559372] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 2.559380] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 2.559390] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.559398] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x40020041 [ 2.559407] [drm:dpu_reg_write] *ERROR* [INTF_TIMING_ENGINE_EN:0x0] <= 0x1 [ 2.559416] DPU:KMS: dpu_kms_wait_flush [ 2.559418] DPU:KMS: dpu_kms_wait_for_commit_done [ 2.559420] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 2.559426] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.559434] DPU:KMS: dpu_kms_complete_comit [ 2.559434] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=1/1 [ 2.559436] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 2.559449] [drm:dpu_crtc_complete_commit] crtc63: send event: (____ptrval____) [ 2.559464] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state (____ptrval____) [ 2.559474] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (4) [ 2.559480] [drm:dpu_crtc_destroy_state] crtc63 [ 2.559496] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state (____ptrval____) [ 2.559518] fb0: Framebuffer is not in virtual address space. [ 2.559536] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state (____ptrval____) [ 2.559544] [drm:dpu_plane_duplicate_state] plane33 [ 2.559541] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x14] [ 2.559551] [drm:drm_mode_object_get] OBJ ID: 64 (2) [ 2.559559] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x10] [ 2.559559] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] (____ptrval____) state to (____ptrval____) [ 2.559574] [drm:drm_mode_object_get] OBJ ID: 65 (1) [ 2.559572] [drm:dpu_reg_write] *ERROR* [intr->intr_set[reg_idx].clr_off:0x18] <= 0x8000000 [ 2.559580] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] (____ptrval____) state to (____ptrval____) [ 2.559592] [drm:dpu_plane_duplicate_state] plane39 [ 2.559592] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.559598] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] (____ptrval____) state to (____ptrval____) [ 2.559610] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state (____ptrval____) [ 2.559607] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,7)@ 2.553439 -> 2.553379 [e 12 us, 0 rep] [ 2.559618] [drm:dpu_plane_duplicate_state] plane45 [ 2.559624] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] (____ptrval____) state to (____ptrval____) [ 2.559636] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state (____ptrval____) [ 2.559634] msm_dpu 1a01000.display-controller: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=1, diff=1, hw=1 hw_last=0 [ 2.559643] [drm:dpu_plane_duplicate_state] plane51 [ 2.559649] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] (____ptrval____) state to (____ptrval____) [ 2.559657] msm_dpu 1a01000.display-controller: [drm:vblank_disable_fn] disabling vblank on crtc 0 [ 2.559660] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state (____ptrval____) [ 2.559668] [drm:dpu_plane_duplicate_state] plane57 [ 2.559668] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.559674] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] (____ptrval____) state to (____ptrval____) [ 2.559685] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state (____ptrval____) [ 2.559681] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,16)@ 2.553515 -> 2.553378 [e 12 us, 0 rep] [ 2.559694] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state (____ptrval____) [ 2.559702] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 2.559707] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 2.559705] msm_dpu 1a01000.display-controller: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=2, diff=0, hw=1 hw_last=1 [ 2.559714] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to (____ptrval____) [ 2.559725] [drm:drm_mode_object_get] OBJ ID: 32 (4) [ 2.559724] msm_dpu 1a01000.display-controller: [drm:msm_crtc_disable_vblank] crtc=63 [ 2.559730] [drm:drm_mode_object_get] OBJ ID: 32 (5) [ 2.559737] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] (____ptrval____) state to (____ptrval____) [ 2.559744] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (5) [ 2.559743] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.559749] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state (____ptrval____) to [NOCRTC] [ 2.559758] [drm:drm_mode_object_get] OBJ ID: 32 (4) [ 2.559763] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state (____ptrval____) to [CRTC:63:crtc-0] [ 2.559764] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xC] [ 2.559771] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking (____ptrval____) [ 2.559779] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 2.559777] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x8] [ 2.559784] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 2.559788] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 2.559789] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x20] [ 2.559792] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 2.559798] msm_dpu 1a01000.display-controller: [drm] refcount=3 [ 2.559803] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 2.559802] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x1C] [ 2.559809] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 2.559814] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 2.559814] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x6A9C4] [ 2.559819] msm_dpu 1a01000.display-controller: [drm] layers: [ 2.559824] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 2.559829] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 2.559826] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x6A9C0] [ 2.559834] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 2.559839] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 2.559839] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x6B1C4] [ 2.559844] msm_dpu 1a01000.display-controller: [drm] name=0 [ 2.559850] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 2.559855] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 2.559853] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x6B1C0] [ 2.559860] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 2.559865] msm_dpu 1a01000.display-controller: [drm] imported=no [ 2.559870] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 2.559875] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 2.559872] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=0/2 [ 2.559883] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.559890] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.559894] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.559898] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.559902] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.559907] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 2.559911] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 2.559915] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.559919] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.559923] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 2.559929] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 2.559934] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 2.559939] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.559942] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.559946] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.559951] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.559958] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.559954] [drm:dpu_crtc_frame_event_work] crtc63 event:1 ts:2553595259 [ 2.559962] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.559966] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.559970] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.559974] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.559977] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.559981] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 2.559985] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.559989] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.559993] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.559998] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.560002] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 2.560007] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.560010] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.560014] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.560019] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.560025] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.560029] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.560033] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.560037] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.560041] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.560045] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.560050] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 2.560054] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.560058] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.560062] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.560067] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.560072] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 2.560076] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.560080] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.560084] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.560089] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.560095] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.560100] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.560104] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.560108] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.560112] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.560116] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.560120] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 2.560125] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.560129] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.560133] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.560138] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.560143] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 2.560147] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.560151] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.560155] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.560160] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.560166] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.560170] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.560174] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.560179] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.560183] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.560187] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.560191] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 2.560196] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.560200] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.560204] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.560208] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.560213] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 2.560218] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 2.560222] msm_dpu 1a01000.display-controller: [drm] active=1 [ 2.560226] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 2.560230] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 2.560234] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 2.560238] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 2.560242] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 2.560246] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.560250] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 2.560254] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 2.560259] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 2.560263] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 2.560272] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 2.560277] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 2.560282] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 2.560286] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 2.560290] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 2.560294] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 2.560299] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 2.560304] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking (____ptrval____) [ 2.560314] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 2.560327] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 2.560337] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to (____ptrval____) [ 2.560346] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object (____ptrval____) state (____ptrval____) to (____ptrval____) [ 2.560354] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to (____ptrval____) [ 2.560363] [drm:dpu_encoder_virt_atomic_check] enc31 [ 2.560370] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object (____ptrval____) state (____ptrval____) to (____ptrval____) [ 2.560382] [drm:dpu_crtc_atomic_check] crtc63: check [ 2.560393] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 2.560404] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 2.560412] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 2.560422] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing (____ptrval____) [ 2.560431] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 2.560440] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 2.560454] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.560463] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,107)@ 2.554297 -> 2.553378 [e 8 us, 0 rep] [ 2.560481] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.560490] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,110)@ 2.554325 -> 2.553380 [e 8 us, 0 rep] [ 2.560505] DPU:KMS: dpu_kms_enable_commit [ 2.560508] DPU:KMS: dpu_kms_wait_flush [ 2.560510] DPU:KMS: dpu_kms_wait_for_commit_done [ 2.560512] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 2.560518] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.560528] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 2.560540] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 2.560551] [drm:dpu_crtc_atomic_begin] crtc63 [ 2.560560] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.560568] [drm:_dpu_crtc_blend_setup] crtc63 [ 2.560577] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 2.560585] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 2.560594] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 2.560602] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 2.560610] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 2.560618] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 2.560625] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 2.560633] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 2.560641] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 2.560650] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 2.560662] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 2.560670] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 2.560678] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 2.560687] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 2.560698] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 2.560706] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 2.560714] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 2.560722] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 2.560730] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 2.560738] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 2.560748] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 2.560757] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 2.560765] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 2.560772] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 2.560781] [drm:dpu_plane_atomic_update] plane33 [ 2.560787] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 2.560801] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 2.560809] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 2.560817] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 2.560825] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 2.560833] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 2.560841] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 2.560849] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 2.560857] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 2.560865] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 2.560873] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 2.560883] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 2.560891] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 2.560899] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 2.560907] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 2.560915] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 2.560923] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 2.560931] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 2.560939] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 2.560947] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 2.560955] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 2.560963] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 2.560971] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 2.560979] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 2.560986] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 2.560994] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 2.561003] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 2.561011] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 2.561020] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.561027] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 2.561035] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 2.561042] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 2.561051] [drm:dpu_crtc_atomic_flush] crtc63 [ 2.561060] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 2.561069] [drm:dpu_core_perf_crtc_update] crtc=63 p=1 new_bw=502848000,old_bw=0 [ 2.561081] msm_dpu 1a01000.display-controller: [drm:msm_crtc_enable_vblank] crtc=63 [ 2.561092] msm_dpu 1a01000.display-controller: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0 [ 2.561102] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.561111] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,183)@ 2.554945 -> 2.553373 [e 8 us, 0 rep] [ 2.561124] msm_dpu 1a01000.display-controller: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=2, diff=0, hw=1 hw_last=1 [ 2.561135] DPU:KMS: dpu_kms_flush_commit [ 2.561137] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561145] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561216] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561229] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=1/1 [ 2.561287] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561356] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561424] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561491] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561559] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561627] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561694] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561762] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561830] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561898] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.561965] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562033] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562100] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562170] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562238] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562306] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562374] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562442] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562509] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562577] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562644] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562712] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562779] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562848] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562915] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.562983] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.563050] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.563118] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.563185] hw recovery is not complete for ctl:1 [ 2.563189] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 2.563200] [drm:dpu_reg_write] *ERROR* [reg->en_off:0x10] <= 0x4000000 [ 2.563209] [drm:dpu_reg_write] *ERROR* [reg->clr_off:0x18] <= 0x8000000 [ 2.563218] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 2.563223] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 2.563228] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 2.563236] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 2.563243] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 2.563252] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.563259] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 2.563268] DPU:KMS: dpu_kms_wait_flush [ 2.563270] DPU:KMS: dpu_kms_wait_for_commit_done [ 2.563272] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 2.563278] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.563286] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.563524] DPU:KMS: mdp_snapshot: START [ 2.564463] DPU:KMS: mdp_snapshot: DONE [ 2.570181] ------------[ cut here ]------------ [ 2.570184] Unbalanced enable for IRQ 42 [ 2.570197] WARNING: CPU: 4 PID: 124 at kernel/irq/manage.c:793 __enable_irq+0x4c/0x7c [ 2.570209] Modules linked in: [ 2.570216] CPU: 4 PID: 124 Comm: kworker/4:4 Not tainted 6.8.0-postmarketos-qcom-msm8976 #140 [ 2.570222] Hardware name: Leeco Le S2 (DT) [ 2.570226] Workqueue: events wled_ovp_work [ 2.570236] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 2.570242] pc : __enable_irq+0x4c/0x7c [ 2.570248] lr : __enable_irq+0x4c/0x7c [ 2.570252] sp : ffff80008277bd60 [ 2.570255] x29: ffff80008277bd60 x28: 0000000000000000 x27: 0000000000000000 [ 2.570265] x26: 0000000000000000 x25: ffff00002383e100 x24: ffff000022020805 [ 2.570274] x23: 0000000000000000 x22: ffff0000df9acb00 x21: ffff000022020800 [ 2.570283] x20: 000000000000002a x19: ffff000023bba800 x18: ffffffffffffffff [ 2.570292] x17: 73204e4f206e6920 x16: 6372202c313a746e x15: ffffffffffffffff [ 2.570301] x14: 0000000000000000 x13: ffff0000d8400000 x12: 000000000000eca6 [ 2.570310] x11: 0000000000004ee2 x10: ffff0000d9a00000 x9 : ffff0000d8400000 [ 2.570319] x8 : 00000000fffbffff x7 : ffff0000d9a00000 x6 : 80000000fffc0000 [ 2.570328] x5 : 0000000000000000 x4 : 0000000000000000 x3 : 00000000ffffffff [ 2.570337] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000025066300 [ 2.570346] Call trace: [ 2.570349] __enable_irq+0x4c/0x7c [ 2.570354] enable_irq+0x4c/0xa4 [ 2.570359] wled_ovp_work+0x14/0x20 [ 2.570365] process_one_work+0x148/0x29c [ 2.570372] worker_thread+0x2fc/0x40c [ 2.570378] kthread+0x110/0x114 [ 2.570386] ret_from_fork+0x10/0x20 [ 2.570392] ---[ end trace 0000000000000000 ]--- [ 2.618335] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.618347] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.618355] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 2.618361] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 2.618367] DPU:KMS: dpu_kms_complete_comit [ 2.618369] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 2.618380] [drm:dpu_crtc_complete_commit] crtc63: send event: (____ptrval____) [ 2.618390] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 2.618401] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state (____ptrval____) [ 2.618409] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (5) [ 2.618416] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (4) [ 2.618422] [drm:dpu_crtc_destroy_state] crtc63 [ 2.618431] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (2) [ 2.618437] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (3) [ 2.618446] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state (____ptrval____) [ 2.618593] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state (____ptrval____) [ 2.618604] [drm:drm_mode_object_get] OBJ ID: 65 (1) [ 2.618612] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] (____ptrval____) state to (____ptrval____) [ 2.618625] [drm:dpu_plane_duplicate_state] plane33 [ 2.618632] [drm:drm_mode_object_get] OBJ ID: 64 (2) [ 2.618638] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] (____ptrval____) state to (____ptrval____) [ 2.618650] [drm:dpu_plane_duplicate_state] plane39 [ 2.618655] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] (____ptrval____) state to (____ptrval____) [ 2.618666] [drm:dpu_plane_duplicate_state] plane45 [ 2.618672] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] (____ptrval____) state to (____ptrval____) [ 2.618682] [drm:dpu_plane_duplicate_state] plane51 [ 2.618688] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] (____ptrval____) state to (____ptrval____) [ 2.618698] [drm:dpu_plane_duplicate_state] plane57 [ 2.618703] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] (____ptrval____) state to (____ptrval____) [ 2.618715] [drm:drm_mode_object_get] OBJ ID: 32 (4) [ 2.618720] [drm:drm_mode_object_get] OBJ ID: 32 (5) [ 2.618725] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] (____ptrval____) state to (____ptrval____) [ 2.618750] device: 'devcd1': device_add [ 2.618789] PM: Adding info for No Bus:devcd1 [ 2.618967] DPU:KMS: mdp_snapshot: START [ 2.619839] DPU:KMS: mdp_snapshot: DONE [ 2.619844] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state (____ptrval____) [ 2.619852] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 2.619858] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] (____ptrval____) state to (____ptrval____) [ 2.619869] [drm:dpu_plane_duplicate_state] plane33 [ 2.619875] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 2.619880] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] (____ptrval____) state to (____ptrval____) [ 2.619891] [drm:dpu_plane_duplicate_state] plane39 [ 2.619897] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] (____ptrval____) state to (____ptrval____) [ 2.619907] [drm:dpu_plane_duplicate_state] plane45 [ 2.619913] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] (____ptrval____) state to (____ptrval____) [ 2.619923] [drm:dpu_plane_duplicate_state] plane51 [ 2.619928] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] (____ptrval____) state to (____ptrval____) [ 2.619939] [drm:dpu_plane_duplicate_state] plane57 [ 2.619944] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] (____ptrval____) state to (____ptrval____) [ 2.619955] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 2.619960] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 2.619965] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] (____ptrval____) state to (____ptrval____) [ 2.619977] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state (____ptrval____) [ 2.619983] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 2.619988] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 2.619993] [drm:dpu_crtc_destroy_state] crtc63 [ 2.620002] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 2.620008] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 2.620014] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state (____ptrval____) [ 2.623671] Console: switching to colour frame buffer device 135x120 [ 2.623694] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state (____ptrval____) [ 2.623702] [drm:dpu_plane_duplicate_state] plane33 [ 2.623708] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 2.623714] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] (____ptrval____) state to (____ptrval____) [ 2.623726] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 2.623731] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] (____ptrval____) state to (____ptrval____) [ 2.623743] [drm:dpu_plane_duplicate_state] plane39 [ 2.623748] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] (____ptrval____) state to (____ptrval____) [ 2.623760] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state (____ptrval____) [ 2.623767] [drm:dpu_plane_duplicate_state] plane45 [ 2.623773] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] (____ptrval____) state to (____ptrval____) [ 2.623784] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state (____ptrval____) [ 2.623790] [drm:dpu_plane_duplicate_state] plane51 [ 2.623796] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] (____ptrval____) state to (____ptrval____) [ 2.623807] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state (____ptrval____) [ 2.623814] [drm:dpu_plane_duplicate_state] plane57 [ 2.623819] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] (____ptrval____) state to (____ptrval____) [ 2.623830] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state (____ptrval____) [ 2.623839] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state (____ptrval____) [ 2.623845] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 2.623850] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 2.623856] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to (____ptrval____) [ 2.623865] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 2.623870] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 2.623875] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] (____ptrval____) state to (____ptrval____) [ 2.623882] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 2.623887] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state (____ptrval____) to [NOCRTC] [ 2.623895] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 2.623900] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state (____ptrval____) to [CRTC:63:crtc-0] [ 2.623909] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking (____ptrval____) [ 2.623915] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 2.623920] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 2.623924] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 2.623928] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 2.623934] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 2.623938] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 2.623945] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 2.623950] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 2.623956] msm_dpu 1a01000.display-controller: [drm] layers: [ 2.623960] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 2.623965] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 2.623970] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 2.623975] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 2.623980] msm_dpu 1a01000.display-controller: [drm] name=0 [ 2.623984] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 2.623989] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 2.623994] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 2.623999] msm_dpu 1a01000.display-controller: [drm] imported=no [ 2.624004] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 2.624010] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 2.624018] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.624022] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.624027] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.624032] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.624036] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.624040] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 2.624045] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 2.624049] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.624053] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.624058] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 2.624063] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 2.624067] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 2.624072] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.624075] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.624079] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.624084] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.624090] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.624094] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.624098] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.624102] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.624106] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.624111] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.624115] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 2.624119] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.624123] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.624127] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.624132] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.624137] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 2.624141] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.624145] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.624149] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.624154] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.624161] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.624165] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.624169] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.624173] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.624178] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.624182] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.624186] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 2.624190] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.624194] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.624198] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.624203] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.624208] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 2.624213] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.624216] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.624220] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.624225] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.624232] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.624236] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.624240] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.624244] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.624248] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.624252] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.624257] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 2.624261] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.624265] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.624270] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.624274] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.624279] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 2.624283] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.624287] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.624291] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.624296] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.624302] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.624307] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.624311] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.624315] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.624319] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.624323] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.624328] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 2.624332] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.624336] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.624340] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.624345] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.624350] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 2.624354] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 2.624358] msm_dpu 1a01000.display-controller: [drm] active=1 [ 2.624362] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 2.624367] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 2.624371] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 2.624375] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 2.624379] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 2.624384] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.624388] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 2.624392] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 2.624396] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 2.624401] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 2.624410] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 2.624415] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 2.624420] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 2.624424] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 2.624428] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 2.624432] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 2.624436] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 2.624441] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking (____ptrval____) [ 2.624450] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 2.624460] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 2.624471] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to (____ptrval____) [ 2.624480] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object (____ptrval____) state (____ptrval____) to (____ptrval____) [ 2.624488] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to (____ptrval____) [ 2.624497] [drm:dpu_encoder_virt_atomic_check] enc31 [ 2.624504] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object (____ptrval____) state (____ptrval____) to (____ptrval____) [ 2.624516] [drm:dpu_crtc_atomic_check] crtc63: check [ 2.624526] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 2.624537] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 2.624545] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 2.624556] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing (____ptrval____) [ 2.624564] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 2.624573] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 2.624586] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.624596] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1752)@ 2.618430 -> 2.603379 [e 8 us, 0 rep] [ 2.624614] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.624623] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1755)@ 2.618458 -> 2.603380 [e 8 us, 0 rep] [ 2.624640] DPU:KMS: dpu_kms_enable_commit [ 2.624643] DPU:KMS: dpu_kms_wait_flush [ 2.624645] DPU:KMS: dpu_kms_wait_for_commit_done [ 2.624647] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 2.624653] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.624662] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.650319] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 2.650539] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:2644164738 [ 2.650729] DPU:KMS: mdp_snapshot: START [ 2.651651] DPU:KMS: mdp_snapshot: DONE [ 2.678333] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.678346] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.678354] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 2.678360] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 2.678367] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 2.678381] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 2.678392] [drm:dpu_crtc_atomic_begin] crtc63 [ 2.678401] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.678409] [drm:_dpu_crtc_blend_setup] crtc63 [ 2.678420] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 2.678429] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 2.678437] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 2.678444] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 2.678452] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 2.678459] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 2.678467] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 2.678474] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 2.678482] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 2.678490] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 2.678501] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 2.678509] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 2.678517] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 2.678525] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 2.678536] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 2.678545] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 2.678553] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 2.678560] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 2.678568] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 2.678576] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 2.678586] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 2.678594] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 2.678601] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 2.678609] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 2.678618] [drm:dpu_plane_atomic_update] plane33 [ 2.678624] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 2.678639] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 2.678648] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 2.678656] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 2.678664] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 2.678672] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 2.678680] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 2.678688] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 2.678696] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 2.678704] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 2.678711] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 2.678720] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 2.678729] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 2.678737] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 2.678745] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 2.678753] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 2.678761] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 2.678769] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 2.678776] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 2.678784] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 2.678792] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 2.678800] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 2.678808] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 2.678816] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 2.678824] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 2.678831] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 2.678840] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 2.678848] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 2.678856] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.678865] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 2.678872] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 2.678879] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 2.678889] [drm:dpu_crtc_atomic_flush] crtc63 [ 2.678897] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 2.678910] DPU:KMS: dpu_kms_flush_commit [ 2.678912] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.678921] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.678991] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679060] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679128] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679196] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679264] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679331] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679399] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679466] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679534] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679603] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679671] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679738] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679806] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679873] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.679941] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680009] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680076] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680144] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680212] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680280] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680347] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680415] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680483] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680550] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680618] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680686] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680754] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680821] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680889] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.680957] hw recovery is not complete for ctl:1 [ 2.680960] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 2.680968] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 2.680975] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 2.680981] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 2.680990] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 2.680997] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 2.681007] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.681015] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 2.681024] DPU:KMS: dpu_kms_wait_flush [ 2.681027] DPU:KMS: dpu_kms_wait_for_commit_done [ 2.681029] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 2.681035] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.681043] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.734332] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.734344] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.734353] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 2.734358] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 2.734363] DPU:KMS: dpu_kms_complete_comit [ 2.734365] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 2.734376] [drm:dpu_crtc_complete_commit] crtc63: send event: (____ptrval____) [ 2.734385] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 2.734395] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state (____ptrval____) [ 2.734402] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 2.734408] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 2.734414] [drm:dpu_crtc_destroy_state] crtc63 [ 2.734423] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 2.734428] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 2.734436] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state (____ptrval____) [ 2.734583] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state (____ptrval____) [ 2.734594] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 2.734602] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] (____ptrval____) state to (____ptrval____) [ 2.734615] [drm:dpu_plane_duplicate_state] plane33 [ 2.734622] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 2.734628] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] (____ptrval____) state to (____ptrval____) [ 2.734639] [drm:dpu_plane_duplicate_state] plane39 [ 2.734645] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] (____ptrval____) state to (____ptrval____) [ 2.734656] [drm:dpu_plane_duplicate_state] plane45 [ 2.734661] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] (____ptrval____) state to (____ptrval____) [ 2.734672] [drm:dpu_plane_duplicate_state] plane51 [ 2.734677] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] (____ptrval____) state to (____ptrval____) [ 2.734687] [drm:dpu_plane_duplicate_state] plane57 [ 2.734693] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] (____ptrval____) state to (____ptrval____) [ 2.734704] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 2.734710] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 2.734715] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] (____ptrval____) state to (____ptrval____) [ 2.734731] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state (____ptrval____) [ 2.734737] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 2.734742] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 2.734747] [drm:dpu_crtc_destroy_state] crtc63 [ 2.734756] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 2.734761] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 2.734767] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state (____ptrval____) [ 2.734943] DPU:KMS: mdp_snapshot: START [ 2.735808] DPU:KMS: mdp_snapshot: DONE [ 2.735813] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state (____ptrval____) [ 2.735819] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 2.735825] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] (____ptrval____) state to (____ptrval____) [ 2.735836] [drm:dpu_plane_duplicate_state] plane33 [ 2.735841] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 2.735846] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] (____ptrval____) state to (____ptrval____) [ 2.735857] [drm:dpu_plane_duplicate_state] plane39 [ 2.735862] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] (____ptrval____) state to (____ptrval____) [ 2.735873] [drm:dpu_plane_duplicate_state] plane45 [ 2.735878] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] (____ptrval____) state to (____ptrval____) [ 2.735888] [drm:dpu_plane_duplicate_state] plane51 [ 2.735894] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] (____ptrval____) state to (____ptrval____) [ 2.735904] [drm:dpu_plane_duplicate_state] plane57 [ 2.735910] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] (____ptrval____) state to (____ptrval____) [ 2.735920] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 2.735925] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 2.735930] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] (____ptrval____) state to (____ptrval____) [ 2.735941] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state (____ptrval____) [ 2.735947] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 2.735951] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 2.735956] [drm:dpu_crtc_destroy_state] crtc63 [ 2.735965] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 2.735970] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 2.735975] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state (____ptrval____) [ 2.766205] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 2.766363] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:2760049113 [ 2.766411] msm_dpu 1a01000.display-controller: [drm] fb0: msmdrmfb frame buffer device [ 2.800466] [drm:dsi_host_attach] id=0 [ 2.800483] driver: 'panel-boe-nt35596s-5p5boe-vdo': driver_bound: bound to device '1a94000.dsi.0' [ 2.800505] panel-boe-nt35596s-5p5boe-vdo 1a94000.dsi.0: Dropping the link to 1a94000.dsi [ 2.800512] device: 'platform:1a94000.dsi--mipi-dsi:1a94000.dsi.0': device_unregister [ 2.800603] msm_dpu 1a01000.display-controller: [drm:drm_fb_helper_hotplug_event] [ 2.800624] [drm:drm_client_modeset_probe] [ 2.800631] bus: 'mipi-dsi': really_probe: bound device 1a94000.dsi.0 to driver panel-boe-nt35596s-5p5boe-vdo [ 2.800635] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 2.800645] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:32:DSI-1] [ 2.800658] driver: 'msm_dsi': driver_bound: bound to device '1a94000.dsi' [ 2.800679] msm_dsi 1a94000.dsi: Dropping the link to 1a01000.display-controller [ 2.800683] device: 'platform:1a01000.display-controller--platform:1a94000.dsi': device_unregister [ 2.800682] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:32:DSI-1] probed modes : [ 2.800691] [drm:drm_mode_debug_printmodeline] Modeline "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 2.800702] [drm:drm_client_modeset_probe] connector 32 enabled? yes [ 2.800715] [drm:drm_client_modeset_probe] Not using firmware configuration [ 2.800723] [drm:drm_client_modeset_probe] looking for cmdline mode on connector 32 [ 2.800730] [drm:drm_client_modeset_probe] looking for preferred mode on connector 32 0 [ 2.800738] [drm:drm_client_modeset_probe] found mode 1080x1920 [ 2.800744] [drm:drm_client_modeset_probe] picking CRTCs for 1080x1920 config [ 2.800754] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 2.800756] msm_dsi 1a94000.dsi: Dropping the link to 200f000.spmi:pmic@3:labibb [ 2.800761] [drm:drm_client_modeset_probe] desired mode 1080x1920 set on crtc 63 (0,0) [ 2.800769] [drm:drm_mode_object_get] OBJ ID: 32 (5) [ 2.800772] device: 'platform:200f000.spmi:pmic@3:labibb--platform:1a94000.dsi': device_unregister [ 2.800775] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 2.800785] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state (____ptrval____) [ 2.800795] [drm:dpu_plane_duplicate_state] plane33 [ 2.800802] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 2.800811] msm_dsi 1a94000.dsi: Dropping the link to 1000000.pinctrl [ 2.800808] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] (____ptrval____) state to (____ptrval____) [ 2.800822] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 2.800829] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] (____ptrval____) state to (____ptrval____) [ 2.800833] device: 'platform:1000000.pinctrl--platform:1a94000.dsi': device_unregister [ 2.800841] [drm:dpu_plane_duplicate_state] plane39 [ 2.800847] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] (____ptrval____) state to (____ptrval____) [ 2.800859] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state (____ptrval____) [ 2.800866] [drm:dpu_plane_duplicate_state] plane45 [ 2.800867] msm_dsi 1a94000.dsi: Dropping the link to 200f000.spmi:pmic@3:leds@d800 [ 2.800872] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] (____ptrval____) state to (____ptrval____) [ 2.800884] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state (____ptrval____) [ 2.800885] device: 'platform:200f000.spmi:pmic@3:leds@d800--platform:1a94000.dsi': device_unregister [ 2.800891] [drm:dpu_plane_duplicate_state] plane51 [ 2.800897] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] (____ptrval____) state to (____ptrval____) [ 2.800908] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state (____ptrval____) [ 2.800916] [drm:dpu_plane_duplicate_state] plane57 [ 2.800924] msm_dsi 1a94000.dsi: Dropping the link to 1a94000.dsi.0 [ 2.800922] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] (____ptrval____) state to (____ptrval____) [ 2.800933] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state (____ptrval____) [ 2.800941] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state (____ptrval____) [ 2.800946] device: 'mipi-dsi:1a94000.dsi.0--platform:1a94000.dsi': device_unregister [ 2.800950] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 2.800955] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 2.800962] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to (____ptrval____) [ 2.800971] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 2.800976] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 2.800982] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] (____ptrval____) state to (____ptrval____) [ 2.800990] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 2.800996] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state (____ptrval____) to [NOCRTC] [ 2.801004] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 2.801009] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state (____ptrval____) to [CRTC:63:crtc-0] [ 2.801018] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking (____ptrval____) [ 2.801025] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 2.801031] bus: 'platform': really_probe: bound device 1a94000.dsi to driver msm_dsi [ 2.801124] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 2.801129] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 2.801193] devices_kset: Moving 78db000.usb to end of list [ 2.801278] PM: Moving platform:78db000.usb to end of list [ 2.801277] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 2.801284] platform 78db000.usb: Retrying from deferred list [ 2.801333] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 2.801427] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 2.801526] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 2.801580] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 2.801616] bus: 'platform': __driver_probe_device: matched device 78db000.usb with driver msm_hsusb [ 2.801677] msm_dpu 1a01000.display-controller: [drm] layers: [ 2.801681] bus: 'platform': really_probe: probing driver msm_hsusb with device 78db000.usb [ 2.801731] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 2.801743] msm_hsusb 78db000.usb: no pinctrl handle [ 2.801829] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 2.801923] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 2.801982] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 2.802081] msm_dpu 1a01000.display-controller: [drm] name=0 [ 2.802135] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 2.802258] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 2.802310] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 2.802411] msm_dpu 1a01000.display-controller: [drm] imported=no [ 2.802508] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 2.802565] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 2.802666] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.802764] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.802819] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.802916] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.803014] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.803069] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 2.803167] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 2.803222] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.803320] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.803418] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 2.803474] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 2.803574] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 2.803629] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.803726] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.803781] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.803879] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.803979] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.804033] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.804129] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.804227] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.804281] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.804378] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.804475] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 2.804529] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.804626] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.804680] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.804777] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.804832] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 2.804929] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.805026] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.805080] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.805178] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.805278] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.805333] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.805430] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.805485] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.805582] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.805679] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.805735] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 2.805832] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.805887] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.805984] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.806083] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.806138] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 2.806243] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.806298] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.806394] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.806449] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.806549] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.806645] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.806700] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.806796] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.806893] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.806947] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.807045] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 2.807100] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.807197] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.807295] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.807350] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.807448] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 2.807503] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 2.807600] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 2.807655] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 2.807710] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 2.807811] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 2.807865] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 2.807962] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 2.808060] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 2.808114] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.808211] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 2.808308] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 2.808363] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 2.808459] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 2.808513] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 2.808610] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 2.808707] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 2.808762] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 2.808858] msm_dpu 1a01000.display-controller: [drm] active=1 [ 2.808912] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 2.809008] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 2.809063] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 2.809160] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 2.809256] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 2.809311] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 2.809408] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 2.809462] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 2.809559] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 2.809614] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 2.809760] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 2.809816] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 2.809913] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 2.809968] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 2.810065] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 2.810119] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 2.810224] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 2.810322] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking (____ptrval____) [ 2.810335] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 2.810353] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 2.810365] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to (____ptrval____) [ 2.810376] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object (____ptrval____) state (____ptrval____) to (____ptrval____) [ 2.810384] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to (____ptrval____) [ 2.810395] [drm:dpu_encoder_virt_atomic_check] enc31 [ 2.810403] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object (____ptrval____) state (____ptrval____) to (____ptrval____) [ 2.810418] [drm:dpu_crtc_atomic_check] crtc63: check [ 2.810429] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 2.810440] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 2.810448] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 2.810460] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing (____ptrval____) [ 2.810470] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 2.810481] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 2.810495] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.810505] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,110)@ 2.804340 -> 2.803395 [e 10 us, 0 rep] [ 2.810576] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.810586] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,120)@ 2.804421 -> 2.803390 [e 9 us, 0 rep] [ 2.810697] DPU:KMS: dpu_kms_enable_commit [ 2.810700] DPU:KMS: dpu_kms_wait_flush [ 2.810754] DPU:KMS: dpu_kms_wait_for_commit_done [ 2.810806] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 2.810906] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.810915] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.814184] Registering platform device 'ci_hdrc.0'. Parent at 78db000.usb [ 2.814286] device: 'ci_hdrc.0': device_add [ 2.814303] bus: 'platform': add device ci_hdrc.0 [ 2.814325] PM: Adding info for platform:ci_hdrc.0 [ 2.814460] bus: 'platform': __driver_probe_device: matched device ci_hdrc.0 with driver ci_hdrc [ 2.814467] bus: 'platform': really_probe: probing driver ci_hdrc with device ci_hdrc.0 [ 2.815285] device: 'ci_hdrc.0.ulpi': device_add [ 2.815308] bus: 'ulpi': add device ci_hdrc.0.ulpi [ 2.815326] PM: Adding info for ulpi:ci_hdrc.0.ulpi [ 2.815357] bus: 'ulpi': __driver_probe_device: matched device ci_hdrc.0.ulpi with driver qcom_usb_hs_phy [ 2.815364] bus: 'ulpi': really_probe: probing driver qcom_usb_hs_phy with device ci_hdrc.0.ulpi [ 2.815373] qcom_usb_hs_phy ci_hdrc.0.ulpi: no pinctrl handle [ 2.815466] device: 'regulator:regulator.44--ulpi:ci_hdrc.0.ulpi': device_add [ 2.815505] devices_kset: Moving ci_hdrc.0.ulpi to end of list [ 2.815509] PM: Moving ulpi:ci_hdrc.0.ulpi to end of list [ 2.815514] qcom_usb_hs_phy ci_hdrc.0.ulpi: Linked as a consumer to regulator.44 [ 2.815570] device: 'regulator:regulator.50--ulpi:ci_hdrc.0.ulpi': device_add [ 2.815603] devices_kset: Moving ci_hdrc.0.ulpi to end of list [ 2.815607] PM: Moving ulpi:ci_hdrc.0.ulpi to end of list [ 2.815612] qcom_usb_hs_phy ci_hdrc.0.ulpi: Linked as a consumer to regulator.50 [ 2.815665] device: 'phy-ci_hdrc.0.ulpi.0': device_add [ 2.815700] PM: Adding info for No Bus:phy-ci_hdrc.0.ulpi.0 [ 2.815730] driver: 'qcom_usb_hs_phy': driver_bound: bound to device 'ci_hdrc.0.ulpi' [ 2.815753] bus: 'ulpi': really_probe: bound device ci_hdrc.0.ulpi to driver qcom_usb_hs_phy [ 2.815945] device: 'ci_hdrc.0': device_add [ 2.815988] PM: Adding info for No Bus:ci_hdrc.0 [ 2.816022] device: 'gadget.0': device_add [ 2.816033] bus: 'gadget': add device gadget.0 [ 2.816048] PM: Adding info for gadget:gadget.0 [ 2.816058] bus: 'gadget': __driver_probe_device: matched device gadget.0 with driver g_ether [ 2.816065] bus: 'gadget': really_probe: probing driver g_ether with device gadget.0 [ 2.816081] g_ether gadget.0: no default pinctrl state [ 2.816159] device: 'usb0': device_add [ 2.816256] PM: Adding info for No Bus:usb0 [ 2.816469] g_ether gadget.0: HOST MAC 6e:c8:33:58:81:cc [ 2.816534] g_ether gadget.0: MAC 7e:ef:68:b0:98:41 [ 2.816696] g_ether gadget.0: Ethernet Gadget, version: Memorial Day 2008 [ 2.816753] g_ether gadget.0: g_ether ready [ 2.816827] driver: 'g_ether': driver_bound: bound to device 'gadget.0' [ 2.816839] bus: 'gadget': really_probe: bound device gadget.0 to driver g_ether [ 2.817798] l13: voltage operation not allowed [ 2.818361] driver: 'ci_hdrc': driver_bound: bound to device 'ci_hdrc.0' [ 2.818382] bus: 'platform': really_probe: bound device ci_hdrc.0 to driver ci_hdrc [ 2.818410] driver: 'msm_hsusb': driver_bound: bound to device '78db000.usb' [ 2.818416] /soc@0/usb@78db000 Dropping the fwnode link to /soc@0/usb@78db000/ulpi/phy [ 2.818456] bus: 'platform': really_probe: bound device 78db000.usb to driver msm_hsusb [ 2.818996] bus: 'platform': add driver gpio-keys [ 2.819072] bus: 'platform': __driver_probe_device: matched device gpio_keys with driver gpio-keys [ 2.819080] bus: 'platform': really_probe: probing driver gpio-keys with device gpio_keys [ 2.819092] gpio-keys gpio_keys: no pinctrl handle [ 2.819658] device: 'input2': device_add [ 2.819723] PM: Adding info for No Bus:input2 [ 2.819751] input: gpio_keys as /devices/platform/gpio_keys/input/input2 [ 2.819826] device: 'event2': device_add [ 2.819846] PM: Adding info for No Bus:event2 [ 2.820137] device: 'wakeup4': device_add [ 2.820181] driver: 'gpio-keys': driver_bound: bound to device 'gpio_keys' [ 2.820194] gpio-keys gpio_keys: Dropping the link to 1000000.pinctrl [ 2.820200] device: 'platform:1000000.pinctrl--platform:gpio_keys': device_unregister [ 2.820292] bus: 'platform': really_probe: bound device gpio_keys to driver gpio-keys [ 2.820359] Extended deferred probe timeout by 10 secs [ 2.820469] cfg80211: Loading compiled-in X.509 certificates for regulatory database [ 2.822459] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' [ 2.823027] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600' [ 2.823122] bus: 'amba': add driver amba-proxy [ 2.823150] Extended deferred probe timeout by 10 secs [ 2.823155] clk: Disabling unused clocks [ 2.823481] PM: genpd: Disabling unused power domains [ 2.823643] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 [ 2.823739] cfg80211: failed to load regulatory.db [ 2.826125] ALSA device list: [ 2.826248] No soundcards found. [ 2.826325] Warning: unable to open an initial console. [ 2.827885] Freeing unused kernel memory: 4608K [ 2.828097] Run /init as init process [ 2.828153] with arguments: [ 2.828155] /init [ 2.828159] PMOS_NO_OUTPUT_REDIRECT [ 2.828162] earlyprintk [ 2.828165] with environment: [ 2.828168] HOME=/ [ 2.828171] TERM=linux [ 2.870357] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.870387] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.870463] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 2.870611] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 2.870709] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 2.870729] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 2.870742] [drm:dpu_crtc_atomic_begin] crtc63 [ 2.870753] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.870762] [drm:_dpu_crtc_blend_setup] crtc63 [ 2.870819] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 2.870919] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 2.870977] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 2.871072] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 2.871167] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 2.871223] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 2.871319] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 2.871374] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 2.871473] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 2.871574] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 2.871586] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 2.871645] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 2.871745] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 2.871847] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 2.871861] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 2.871870] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 2.872020] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 2.872083] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 2.872098] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 2.872246] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 2.872255] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 2.872355] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 2.872414] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 2.872515] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 2.872617] [drm:dpu_plane_atomic_update] plane33 [ 2.872627] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 2.872642] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 2.872701] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 2.872802] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 2.872903] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 2.872961] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 2.873062] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 2.873120] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 2.873221] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 2.873321] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 2.873378] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 2.873480] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 2.873539] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 2.873639] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 2.873739] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 2.873797] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 2.873897] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 2.873997] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 2.874056] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 2.874157] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 2.874284] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 2.874294] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 2.874353] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 2.874503] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 2.874605] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 2.874703] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 2.874759] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 2.874768] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 2.874913] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 2.874922] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 2.875016] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 2.875024] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 2.875166] [drm:dpu_crtc_atomic_flush] crtc63 [ 2.875176] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 2.875190] DPU:KMS: dpu_kms_flush_commit [ 2.875194] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.875251] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.875411] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.875531] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.875685] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.875802] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.875960] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.876075] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.876233] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.876348] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.876507] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.876624] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.876782] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.876893] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.877046] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.877161] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 2.877310] hw recovery is not complete for ctl:1 [ 2.877414] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 2.877518] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 2.877526] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 2.877532] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 2.877541] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 2.877640] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 2.877790] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.877798] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 2.877942] DPU:KMS: dpu_kms_wait_flush [ 2.877945] DPU:KMS: dpu_kms_wait_for_commit_done [ 2.877996] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 2.878093] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.878101] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.878336] DPU:KMS: mdp_snapshot: START [ 2.879345] DPU:KMS: mdp_snapshot: DONE [ 2.930332] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.930398] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 2.930494] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 2.930641] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 2.930740] DPU:KMS: dpu_kms_complete_comit [ 2.930743] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 2.930806] [drm:dpu_crtc_complete_commit] crtc63: send event: (____ptrval____) [ 2.930820] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 2.930835] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state (____ptrval____) [ 2.930846] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 2.930855] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 2.930861] [drm:dpu_crtc_destroy_state] crtc63 [ 2.930871] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 2.930878] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 2.930889] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state (____ptrval____) [ 2.930907] msm_dpu 1a01000.display-controller: [drm:drm_client_dev_hotplug] fbdev: ret=0 [ 2.930929] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state (____ptrval____) [ 2.930939] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 2.930945] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] (____ptrval____) state to (____ptrval____) [ 2.930959] [drm:dpu_plane_duplicate_state] plane33 [ 2.930966] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 2.930971] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] (____ptrval____) state to (____ptrval____) [ 2.930984] [drm:dpu_plane_duplicate_state] plane39 [ 2.930990] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] (____ptrval____) state to (____ptrval____) [ 2.931002] [drm:dpu_plane_duplicate_state] plane45 [ 2.931008] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] (____ptrval____) state to (____ptrval____) [ 2.931020] [drm:dpu_plane_duplicate_state] plane51 [ 2.931026] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] (____ptrval____) state to (____ptrval____) [ 2.931038] [drm:dpu_plane_duplicate_state] plane57 [ 2.931044] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] (____ptrval____) state to (____ptrval____) [ 2.931057] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 2.931062] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 2.931068] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] (____ptrval____) state to (____ptrval____) [ 2.931092] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state (____ptrval____) [ 2.931099] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 2.931104] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 2.931110] [drm:dpu_crtc_destroy_state] crtc63 [ 2.931119] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 2.931125] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 2.931131] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state (____ptrval____) [ 2.962328] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 2.962585] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:2956269842 [ 3.618455] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state (____ptrval____) [ 3.618479] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 3.618490] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] (____ptrval____) state to (____ptrval____) [ 3.618508] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to (____ptrval____) [ 3.618520] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 3.618527] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 3.618533] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] (____ptrval____) state to (____ptrval____) [ 3.618542] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state (____ptrval____) [ 3.618550] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 3.618556] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 3.618561] [drm:dpu_crtc_destroy_state] crtc63 [ 3.618573] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 3.618578] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state (____ptrval____) [ 6.338508] cpu cpu0: _set_opp: switching OPP: Freq 1017600000 -> 200000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 6.338892] cpu cpu4: _set_opp: switching OPP: Freq 1190400000 -> 400000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 10.658116] cpu cpu4: _set_opp: switching OPP: Freq 400000000 -> 1190400000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 12.019329] cpu cpu0: _set_opp: switching OPP: Freq 200000000 -> 800000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 14.961075] cpu cpu4: _set_opp: switching OPP: Freq 1190400000 -> 1612800000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 16.314434] cpu cpu0: _set_opp: switching OPP: Freq 800000000 -> 200000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 19.259438] cpu cpu4: _set_opp: switching OPP: Freq 1612800000 -> 1190400000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 20.609574] cpu cpu0: _set_opp: switching OPP: Freq 200000000 -> 400000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 23.187919] device: 'dm-0': device_add [ 23.188164] PM: Adding info for No Bus:dm-0 [ 23.188873] device: '252:0': device_add [ 23.189009] PM: Adding info for No Bus:252:0 [ 23.192199] device: 'dm-1': device_add [ 23.192442] PM: Adding info for No Bus:dm-1 [ 23.192957] device: '252:1': device_add [ 23.193088] PM: Adding info for No Bus:252:1 [ 23.556882] cpu cpu4: _set_opp: switching OPP: Freq 1190400000 -> 1747200000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 23.774286] random: crng init done [ 24.907653] cpu cpu0: _set_opp: switching OPP: Freq 400000000 -> 800000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 25.769035] bus: 'gadget': add driver configfs-gadget.g1 [ 25.769097] UDC core: g1: couldn't find an available UDC or it's busy [ 25.769184] bus: 'gadget': remove driver configfs-gadget.g1 [ 25.769198] driver: 'configfs-gadget.g1': driver_release [ 27.663050] EXT4-fs (dm-0): mounted filesystem 22e649ed-40f8-452f-8148-3eccf32131c8 ro without journal. Quota mode: none. [ 27.858402] cpu cpu4: _set_opp: switching OPP: Freq 1747200000 -> 400000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 29.203044] cpu cpu0: _set_opp: switching OPP: Freq 800000000 -> 200000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 33.074020] cpu cpu4: _set_opp: switching OPP: Freq 400000000 -> 1190400000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 33.142498] EXT4-fs (dm-1): INFO: recovery required on readonly filesystem [ 33.142821] EXT4-fs (dm-1): write access will be enabled during recovery [ 33.498718] cpu cpu0: _set_opp: switching OPP: Freq 200000000 -> 400000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 33.822563] EXT4-fs (dm-1): orphan cleanup on readonly fs [ 33.824749] EXT4-fs (dm-1): recovery complete [ 33.827177] EXT4-fs (dm-1): mounted filesystem 63369415-d83e-41d9-b7c0-ae33d07fa984 ro with ordered data mode. Quota mode: none. [ 33.837385] EXT4-fs (dm-0): unmounting filesystem 22e649ed-40f8-452f-8148-3eccf32131c8. [ 34.799331] EXT4-fs (dm-0): warning: mounting unchecked fs, running e2fsck is recommended [ 34.801862] EXT4-fs (dm-0): mounted filesystem 22e649ed-40f8-452f-8148-3eccf32131c8 r/w without journal. Quota mode: none. [ 37.369459] cpu cpu4: _set_opp: switching OPP: Freq 1190400000 -> 400000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 37.794765] cpu cpu0: _set_opp: switching OPP: Freq 400000000 -> 1017600000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 37.957972] udevd[3105]: starting version 3.2.14 [ 38.031293] udevd[3105]: starting eudev-3.2.14 [ 39.289007] EXT4-fs (dm-1): re-mounted 63369415-d83e-41d9-b7c0-ae33d07fa984 r/w. Quota mode: none. [ 39.334370] EXT4-fs (dm-1): re-mounted 63369415-d83e-41d9-b7c0-ae33d07fa984 r/w. Quota mode: none. [ 39.403653] EXT4-fs (dm-0): re-mounted 22e649ed-40f8-452f-8148-3eccf32131c8 r/w. Quota mode: none. [ 41.664865] cpu cpu4: _set_opp: switching OPP: Freq 400000000 -> 1190400000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 42.090405] cpu cpu0: _set_opp: switching OPP: Freq 1017600000 -> 1401600000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 44.516423] [drm:drm_stub_open] [ 44.516446] msm_dpu 1a01000.display-controller: [drm:drm_open_helper] comm="elogind", pid=3821, minor=0 [ 44.516470] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="elogind" pid=3821, dev=0xe200, auth=1, DRM_IOCTL_SET_MASTER [ 44.517128] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES [ 44.518011] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_VERSION [ 44.518042] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_VERSION [ 44.518092] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 44.518110] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 44.518123] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 44.518138] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_SET_CLIENT_CAP [ 44.518152] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 44.518211] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_SET_CLIENT_CAP [ 44.518239] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 44.518258] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 44.518280] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES [ 44.518301] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES [ 44.518328] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCRTC [ 44.518353] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.518376] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.518399] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518415] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518434] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518448] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518464] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518479] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518495] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518509] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518527] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES [ 44.518544] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES [ 44.518568] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 44.518587] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 44.518605] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.518626] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.518650] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518668] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518687] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518702] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518719] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518734] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518750] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518765] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518781] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518796] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518812] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518826] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518842] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518856] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518873] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518888] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518903] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518918] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518934] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518949] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518965] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518980] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.518995] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519010] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519026] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519040] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519055] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519069] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519085] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519100] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519116] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519132] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519150] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519167] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519186] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519200] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519218] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.519236] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.519296] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.519314] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.519336] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 44.519351] [drm:drm_mode_object_put.part.0] OBJ ID: 34 (2) [ 44.519364] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 44.519378] [drm:drm_mode_object_put.part.0] OBJ ID: 34 (2) [ 44.519406] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 44.519424] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 44.519442] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.519460] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.519481] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519497] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519515] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519530] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519546] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519561] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519577] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519592] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519607] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519622] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519638] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519652] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519668] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519684] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519699] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519714] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519730] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519744] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519760] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519774] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519791] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519805] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519821] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519835] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519851] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519865] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519880] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519895] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519911] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519926] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519942] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519958] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519975] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.519991] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520010] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520025] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520042] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.520060] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.520081] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 44.520097] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 44.520115] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.520133] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.520155] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520171] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520189] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520204] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520219] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520234] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520250] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520265] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520280] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520295] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520311] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520326] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520341] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520356] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520371] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520386] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520402] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520416] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520432] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520447] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520463] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520477] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520493] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520507] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520523] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520537] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520552] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520567] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520583] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520598] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520613] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520629] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520646] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520662] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520682] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520697] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520713] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.520730] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.520751] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 44.520768] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 44.520786] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.520804] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.520825] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520841] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520859] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520874] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520889] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520904] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520920] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520934] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520950] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520965] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520980] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.520995] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521010] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521025] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521041] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521055] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521071] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521086] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521102] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521116] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521132] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521147] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521162] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521176] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521192] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521207] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521222] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521237] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521253] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521267] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521283] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521299] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521318] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521334] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521353] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521367] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521383] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.521401] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.521422] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 44.521439] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 44.521457] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.521476] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.521497] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521513] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521530] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521544] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521560] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521575] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521591] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521606] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521621] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521636] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521651] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521666] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521681] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521696] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521712] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521727] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521743] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521757] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521773] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521787] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521803] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521817] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521833] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521848] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521864] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521878] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521893] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521908] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521924] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521938] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521954] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521971] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.521989] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.522005] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.522024] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.522038] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 44.522054] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.522072] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.522109] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.522127] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 44.522149] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 44.522162] [drm:drm_mode_object_put.part.0] OBJ ID: 58 (2) [ 44.522194] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 44.522208] [drm:drm_mode_object_put.part.0] OBJ ID: 58 (2) [ 44.524725] [drm:drm_stub_open] [ 44.524746] msm_dpu 1a01000.display-controller: [drm:drm_open_helper] comm="phoc", pid=4310, minor=128 [ 44.524776] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 44.524796] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 44.534589] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 44.534625] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 45.383497] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 45.383533] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 45.388485] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 45.388510] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 45.392805] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 45.392828] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 45.392871] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, MSM_GEM_NEW [ 45.392885] msm_dpu 1a01000.display-controller: [drm:msm_gem_new_impl.isra.0] invalid cache flag: 80000 [ 45.392898] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4310, ret=-22 [ 45.396474] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, MSM_GET_PARAM [ 45.396489] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4310, ret=-6 [ 45.396547] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, MSM_GET_PARAM [ 45.396560] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4310, ret=-6 [ 45.396580] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, MSM_GET_PARAM [ 45.396591] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4310, ret=-6 [ 45.396611] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4310, dev=0xe280, auth=0, MSM_GET_PARAM [ 45.396622] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4310, ret=-6 [ 45.404642] msm_dpu 1a01000.display-controller: [drm:drm_release] open_count = 2 [ 45.404668] msm_dpu 1a01000.display-controller: [drm:drm_file_free] comm="phoc", pid=4310, dev=0xe280, open_count=2 [ 45.406286] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="elogind" pid=3821, dev=0xe200, auth=1, DRM_IOCTL_DROP_MASTER [ 45.406331] msm_dpu 1a01000.display-controller: [drm:drm_release] open_count = 1 [ 45.406343] msm_dpu 1a01000.display-controller: [drm:drm_file_free] comm="elogind", pid=3821, dev=0xe200, open_count=1 [ 45.406359] msm_dpu 1a01000.display-controller: [drm:_drm_lease_revoke] revoke leases for 000000008402c5ae 0 [ 45.406373] msm_dpu 1a01000.display-controller: [drm:drm_lease_destroy] drm_lease_destroy 0 [ 45.406383] msm_dpu 1a01000.display-controller: [drm:drm_lease_destroy] drm_lease_destroy done 0 [ 45.406398] msm_dpu 1a01000.display-controller: [drm:drm_lastclose] [ 45.406406] msm_dpu 1a01000.display-controller: [drm:drm_lastclose] driver lastclose completed [ 45.406421] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 00000000c7b1c2b4 [ 45.406431] [drm:dpu_plane_duplicate_state] plane33 [ 45.406441] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 45.406448] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000d7313028 state to 00000000c7b1c2b4 [ 45.406464] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 45.406470] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 00000000ecedc2d0 state to 00000000c7b1c2b4 [ 45.406483] [drm:dpu_plane_duplicate_state] plane39 [ 45.406489] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 0000000060d8ecb2 state to 00000000c7b1c2b4 [ 45.406501] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 0000000060d8ecb2 [ 45.406510] [drm:dpu_plane_duplicate_state] plane45 [ 45.406516] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000fb6dca68 state to 00000000c7b1c2b4 [ 45.406527] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 00000000fb6dca68 [ 45.406535] [drm:dpu_plane_duplicate_state] plane51 [ 45.406542] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000023afd08c state to 00000000c7b1c2b4 [ 45.406553] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 0000000023afd08c [ 45.406562] [drm:dpu_plane_duplicate_state] plane57 [ 45.406568] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000060cca94c state to 00000000c7b1c2b4 [ 45.406579] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 0000000060cca94c [ 45.406591] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 00000000d7313028 [ 45.406598] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 45.406604] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 45.406611] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 00000000c7b1c2b4 [ 45.406622] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.406627] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 45.406633] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 000000008402c5ae state to 00000000c7b1c2b4 [ 45.406641] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.406647] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000008402c5ae to [NOCRTC] [ 45.406656] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.406662] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000008402c5ae to [CRTC:63:crtc-0] [ 45.406671] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 00000000c7b1c2b4 [ 45.406678] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 45.406685] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 45.406689] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 45.406694] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 45.406701] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 45.406707] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 45.406714] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 45.406720] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 45.406725] msm_dpu 1a01000.display-controller: [drm] layers: [ 45.406730] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 45.406737] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 45.406742] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 45.406748] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 45.406754] msm_dpu 1a01000.display-controller: [drm] name=0 [ 45.406759] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 45.406763] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 45.406769] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 45.406774] msm_dpu 1a01000.display-controller: [drm] imported=no [ 45.406779] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 45.406785] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 45.406794] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.406799] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.406804] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.406809] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.406814] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.406819] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 45.406823] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 45.406828] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.406834] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.406838] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 45.406844] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 45.406850] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 45.406855] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.406860] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.406865] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.406871] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.406879] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.406883] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.406888] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.406893] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.406897] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.406902] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.406907] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 45.406912] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.406917] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.406921] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.406927] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.406933] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 45.406938] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.406942] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.406946] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.406952] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.406960] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.406964] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.406969] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.406974] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.406979] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.406983] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.406988] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 45.406993] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.406998] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.407003] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.407008] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.407014] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 45.407019] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.407023] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.407028] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.407033] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.407040] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.407045] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.407050] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.407055] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.407059] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.407064] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.407069] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 45.407074] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.407079] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.407083] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.407089] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.407094] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 45.407099] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.407104] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.407108] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.407114] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.407121] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.407126] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.407130] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.407135] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.407140] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.407145] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.407149] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 45.407154] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.407159] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.407163] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.407168] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.407174] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 45.407179] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 45.407184] msm_dpu 1a01000.display-controller: [drm] active=1 [ 45.407189] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 45.407194] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 45.407199] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 45.407204] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 45.407209] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 45.407214] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.407218] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 45.407223] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 45.407228] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 45.407233] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 45.407244] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 45.407249] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 45.407254] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 45.407259] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 45.407263] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 45.407268] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 45.407273] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 45.407278] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 00000000c7b1c2b4 [ 45.407289] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 45.407301] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 45.407312] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 45.407323] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 00000000f9a77f5f to 00000000c7b1c2b4 [ 45.407332] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 45.407342] [drm:dpu_encoder_virt_atomic_check] enc31 [ 45.407351] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 00000000f8c6cdc2 to 00000000c7b1c2b4 [ 45.407366] [drm:dpu_crtc_atomic_check] crtc63: check [ 45.407380] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 45.407391] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 45.407399] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 45.407411] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 00000000c7b1c2b4 [ 45.407421] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 45.407432] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 45.407448] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.407460] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1397)@ 45.401294 -> 45.389292 [e 12 us, 0 rep] [ 45.407482] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.407491] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1401)@ 45.401326 -> 45.389290 [e 8 us, 0 rep] [ 45.407509] DPU:KMS: dpu_kms_enable_commit [ 45.407514] DPU:KMS: dpu_kms_wait_flush [ 45.407517] DPU:KMS: dpu_kms_wait_for_commit_done [ 45.407520] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 45.407528] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.407536] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.462333] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.462356] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.462365] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 45.462373] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 45.462384] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 45.462400] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 45.462412] [drm:dpu_crtc_atomic_begin] crtc63 [ 45.462425] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.462434] [drm:_dpu_crtc_blend_setup] crtc63 [ 45.462444] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 45.462454] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 45.462463] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 45.462472] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 45.462480] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 45.462488] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 45.462497] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 45.462508] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 45.462516] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 45.462525] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 45.462538] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 45.462547] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 45.462557] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 45.462566] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 45.462580] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 45.462588] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 45.462598] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 45.462609] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 45.462617] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 45.462625] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 45.462636] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 45.462645] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 45.462653] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 45.462662] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 45.462671] [drm:dpu_plane_atomic_update] plane33 [ 45.462680] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 45.462696] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 45.462705] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 45.462714] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 45.462723] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 45.462731] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 45.462741] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 45.462750] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 45.462758] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 45.462767] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 45.462775] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 45.462785] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 45.462794] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 45.462803] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 45.462812] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 45.462821] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 45.462829] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 45.462838] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 45.462847] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 45.462855] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 45.462864] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 45.462872] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 45.462881] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 45.462890] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 45.462899] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 45.462908] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 45.462918] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 45.462926] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 45.462936] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.462945] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 45.462953] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 45.462961] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 45.462971] [drm:dpu_crtc_atomic_flush] crtc63 [ 45.462980] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 45.462994] DPU:KMS: dpu_kms_flush_commit [ 45.462998] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463007] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463077] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463148] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463217] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463286] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463355] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463424] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463493] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463562] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463631] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463699] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463768] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463837] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463905] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.463974] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464043] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464112] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464180] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464249] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464318] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464387] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464456] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464524] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464594] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464662] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464731] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464800] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464869] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.464938] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.465007] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.465075] hw recovery is not complete for ctl:1 [ 45.465081] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 45.465093] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 45.465102] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 45.465108] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 45.465117] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 45.465125] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 45.465136] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.465144] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 45.465154] DPU:KMS: dpu_kms_wait_flush [ 45.465157] DPU:KMS: dpu_kms_wait_for_commit_done [ 45.465160] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 45.465168] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.465177] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.465415] DPU:KMS: mdp_snapshot: START [ 45.466360] DPU:KMS: mdp_snapshot: DONE [ 45.518334] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.518348] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.518357] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 45.518364] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 45.518371] DPU:KMS: dpu_kms_complete_comit [ 45.518374] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 45.518386] [drm:dpu_crtc_complete_commit] crtc63: send event: 000000000aff3ec0 [ 45.518397] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 45.518411] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 45.518421] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.518429] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 45.518435] [drm:dpu_crtc_destroy_state] crtc63 [ 45.518446] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 45.518453] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 45.518463] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 00000000c7b1c2b4 [ 45.518477] msm_dpu 1a01000.display-controller: [drm:drm_client_dev_restore] fbdev: ret=0 [ 45.518615] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009bf3d1f9 [ 45.518630] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 45.518639] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000007027eac state to 000000009bf3d1f9 [ 45.518655] [drm:dpu_plane_duplicate_state] plane33 [ 45.518662] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 45.518668] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000077300e58 state to 000000009bf3d1f9 [ 45.518681] [drm:dpu_plane_duplicate_state] plane39 [ 45.518688] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000257f9ae7 state to 000000009bf3d1f9 [ 45.518699] [drm:dpu_plane_duplicate_state] plane45 [ 45.518705] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000dcf733d9 state to 000000009bf3d1f9 [ 45.518717] [drm:dpu_plane_duplicate_state] plane51 [ 45.518723] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 00000000df8c4384 state to 000000009bf3d1f9 [ 45.518734] [drm:dpu_plane_duplicate_state] plane57 [ 45.518740] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 000000008f52cf7b state to 000000009bf3d1f9 [ 45.518753] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.518759] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 45.518764] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000a402007c state to 000000009bf3d1f9 [ 45.518789] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009bf3d1f9 [ 45.518793] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 00000000c7b1c2b4 [ 45.518796] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.518802] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 45.518804] [drm:dpu_plane_duplicate_state] plane33 [ 45.518807] [drm:dpu_crtc_destroy_state] crtc63 [ 45.518811] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 45.518817] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 45.518817] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000095ea3066 state to 00000000c7b1c2b4 [ 45.518822] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 45.518828] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009bf3d1f9 [ 45.518830] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 45.518836] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000080770e55 state to 00000000c7b1c2b4 [ 45.518847] [drm:dpu_plane_duplicate_state] plane39 [ 45.518854] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000002b5375e3 state to 00000000c7b1c2b4 [ 45.518865] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 000000002b5375e3 [ 45.518873] [drm:dpu_plane_duplicate_state] plane45 [ 45.518878] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000000e620d3d state to 00000000c7b1c2b4 [ 45.518889] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 000000000e620d3d [ 45.518897] [drm:dpu_plane_duplicate_state] plane51 [ 45.518902] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 000000005f998769 state to 00000000c7b1c2b4 [ 45.518913] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 000000005f998769 [ 45.518920] [drm:dpu_plane_duplicate_state] plane57 [ 45.518926] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 00000000d05cc508 state to 00000000c7b1c2b4 [ 45.518937] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 00000000d05cc508 [ 45.518946] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 0000000095ea3066 [ 45.518953] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 45.518958] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 45.518964] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 00000000c7b1c2b4 [ 45.518973] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.518977] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 45.518982] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000011b5ad1 state to 00000000c7b1c2b4 [ 45.518989] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.518995] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000011b5ad1 to [NOCRTC] [ 45.519003] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.519008] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000011b5ad1 to [CRTC:63:crtc-0] [ 45.519016] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 00000000c7b1c2b4 [ 45.519023] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 45.519028] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 45.519032] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 45.519036] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 45.519041] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 45.519046] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 45.519052] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 45.519057] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 45.519062] msm_dpu 1a01000.display-controller: [drm] layers: [ 45.519066] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 45.519071] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 45.519076] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 45.519081] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 45.519086] msm_dpu 1a01000.display-controller: [drm] name=0 [ 45.519091] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 45.519095] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 45.519100] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 45.519104] msm_dpu 1a01000.display-controller: [drm] imported=no [ 45.519109] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 45.519114] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 45.519122] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.519127] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.519132] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.519137] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.519141] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.519146] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 45.519150] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 45.519154] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.519159] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.519163] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 45.519169] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 45.519174] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 45.519179] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.519183] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.519187] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.519192] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.519199] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.519203] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.519207] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.519211] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.519215] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.519220] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.519224] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 45.519227] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.519231] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.519235] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.519240] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.519245] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 45.519249] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.519253] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.519256] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.519261] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.519267] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.519271] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.519275] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.519279] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.519283] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.519287] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.519291] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 45.519295] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.519299] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.519303] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.519307] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.519312] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 45.519316] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.519320] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.519324] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.519329] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.519335] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.519339] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.519343] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.519348] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.519352] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.519356] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.519360] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 45.519364] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.519368] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.519373] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.519377] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.519382] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 45.519386] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.519390] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.519394] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.519399] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.519405] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.519410] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.519414] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.519418] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.519422] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.519426] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.519430] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 45.519434] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.519438] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.519442] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.519448] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.519453] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 45.519457] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 45.519461] msm_dpu 1a01000.display-controller: [drm] active=1 [ 45.519465] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 45.519469] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 45.519474] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 45.519478] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 45.519482] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 45.519486] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.519490] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 45.519495] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 45.519499] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 45.519503] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 45.519512] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 45.519517] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 45.519521] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 45.519526] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 45.519529] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 45.519533] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 45.519538] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 45.519542] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 00000000c7b1c2b4 [ 45.519553] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 45.519564] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 45.519575] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 45.519585] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 00000000e900b734 to 00000000c7b1c2b4 [ 45.519593] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 45.519603] [drm:dpu_encoder_virt_atomic_check] enc31 [ 45.519611] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 000000001169e4eb to 00000000c7b1c2b4 [ 45.519624] [drm:dpu_crtc_atomic_check] crtc63: check [ 45.519635] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 45.519646] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 45.519654] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 45.519664] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 00000000c7b1c2b4 [ 45.519673] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 45.519683] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 45.519697] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.519708] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,882)@ 45.513542 -> 45.505965 [e 11 us, 0 rep] [ 45.519733] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.519742] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,886)@ 45.513576 -> 45.505964 [e 8 us, 0 rep] [ 45.519759] DPU:KMS: dpu_kms_enable_commit [ 45.519763] DPU:KMS: dpu_kms_wait_flush [ 45.519765] DPU:KMS: dpu_kms_wait_for_commit_done [ 45.519767] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 45.519774] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.519782] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.550318] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 45.550488] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:45544165139 [ 45.574340] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.574352] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.574360] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 45.574366] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 45.574375] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 45.574390] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 45.574402] [drm:dpu_crtc_atomic_begin] crtc63 [ 45.574412] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.574421] [drm:_dpu_crtc_blend_setup] crtc63 [ 45.574430] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 45.574440] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 45.574448] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 45.574456] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 45.574464] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 45.574471] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 45.574479] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 45.574488] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 45.574495] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 45.574505] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 45.574517] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 45.574526] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 45.574534] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 45.574542] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 45.574555] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 45.574563] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 45.574572] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 45.574580] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 45.574588] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 45.574595] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 45.574606] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 45.574614] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 45.574622] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 45.574630] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 45.574639] [drm:dpu_plane_atomic_update] plane33 [ 45.574645] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 45.574660] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 45.574669] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 45.574677] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 45.574685] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 45.574694] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 45.574702] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 45.574710] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 45.574718] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 45.574726] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 45.574734] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 45.574744] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 45.574752] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 45.574760] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 45.574769] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 45.574777] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 45.574784] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 45.574792] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 45.574800] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 45.574808] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 45.574817] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 45.574824] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 45.574832] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 45.574841] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 45.574849] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 45.574857] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 45.574865] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 45.574872] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 45.574881] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.574890] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 45.574897] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 45.574905] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 45.574914] [drm:dpu_crtc_atomic_flush] crtc63 [ 45.574922] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 45.574934] DPU:KMS: dpu_kms_flush_commit [ 45.574937] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.574945] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575015] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575085] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575155] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575223] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575291] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575359] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575428] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575496] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575564] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575633] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575701] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575769] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575837] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575905] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.575973] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576041] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576109] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576178] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576247] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576315] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576383] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576451] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576519] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576587] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576655] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576723] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576792] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576860] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576928] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.576995] hw recovery is not complete for ctl:1 [ 45.576999] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 45.577011] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 45.577018] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 45.577024] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 45.577032] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 45.577040] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 45.577050] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.577057] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 45.577067] DPU:KMS: dpu_kms_wait_flush [ 45.577069] DPU:KMS: dpu_kms_wait_for_commit_done [ 45.577071] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 45.577077] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.577086] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.577332] DPU:KMS: mdp_snapshot: START [ 45.578276] DPU:KMS: mdp_snapshot: DONE [ 45.630334] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.630346] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.630355] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 45.630360] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 45.630366] DPU:KMS: dpu_kms_complete_comit [ 45.630368] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 45.630379] [drm:dpu_crtc_complete_commit] crtc63: send event: 000000000aff3ec0 [ 45.630390] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 45.630401] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 45.630409] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.630417] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 45.630422] [drm:dpu_crtc_destroy_state] crtc63 [ 45.630431] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 45.630437] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 45.630445] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 00000000c7b1c2b4 [ 45.630460] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 00000000c7b1c2b4 [ 45.630468] [drm:dpu_plane_duplicate_state] plane33 [ 45.630474] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 45.630478] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000060cca94c state to 00000000c7b1c2b4 [ 45.630492] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 45.630497] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000023afd08c state to 00000000c7b1c2b4 [ 45.630508] [drm:dpu_plane_duplicate_state] plane39 [ 45.630514] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000fb6dca68 state to 00000000c7b1c2b4 [ 45.630525] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 00000000fb6dca68 [ 45.630533] [drm:dpu_plane_duplicate_state] plane45 [ 45.630538] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 0000000060d8ecb2 state to 00000000c7b1c2b4 [ 45.630549] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 0000000060d8ecb2 [ 45.630556] [drm:dpu_plane_duplicate_state] plane51 [ 45.630561] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 00000000d7313028 state to 00000000c7b1c2b4 [ 45.630572] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 00000000d7313028 [ 45.630579] [drm:dpu_plane_duplicate_state] plane57 [ 45.630587] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 00000000ecedc2d0 state to 00000000c7b1c2b4 [ 45.630597] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 00000000ecedc2d0 [ 45.630607] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 0000000060cca94c [ 45.630613] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 45.630618] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 45.630624] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 45.630630] [drm:dpu_crtc_destroy_state] crtc63 [ 45.630639] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 45.630643] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 45.630721] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009bf3d1f9 [ 45.630733] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 45.630741] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000008f52cf7b state to 000000009bf3d1f9 [ 45.630754] [drm:dpu_plane_duplicate_state] plane33 [ 45.630761] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 45.630767] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000df8c4384 state to 000000009bf3d1f9 [ 45.630779] [drm:dpu_plane_duplicate_state] plane39 [ 45.630785] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000dcf733d9 state to 000000009bf3d1f9 [ 45.630796] [drm:dpu_plane_duplicate_state] plane45 [ 45.630802] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000257f9ae7 state to 000000009bf3d1f9 [ 45.630813] [drm:dpu_plane_duplicate_state] plane51 [ 45.630818] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000077300e58 state to 000000009bf3d1f9 [ 45.630829] [drm:dpu_plane_duplicate_state] plane57 [ 45.630835] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000007027eac state to 000000009bf3d1f9 [ 45.630848] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.630853] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 45.630858] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 000000006abce4f0 state to 000000009bf3d1f9 [ 45.630881] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009bf3d1f9 [ 45.630887] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.630893] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 45.630897] [drm:dpu_crtc_destroy_state] crtc63 [ 45.630906] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 45.630911] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 45.630916] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009bf3d1f9 [ 45.631014] [drm:dpu_plane_duplicate_state] plane33 [ 45.631024] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 45.631031] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000ecedc2d0 state to 00000000c7b1c2b4 [ 45.631046] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 45.631052] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 00000000d7313028 state to 00000000c7b1c2b4 [ 45.631064] [drm:dpu_plane_duplicate_state] plane39 [ 45.631071] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 0000000060d8ecb2 state to 00000000c7b1c2b4 [ 45.631082] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 0000000060d8ecb2 [ 45.631089] [drm:dpu_plane_duplicate_state] plane45 [ 45.631095] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000fb6dca68 state to 00000000c7b1c2b4 [ 45.631106] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 00000000fb6dca68 [ 45.631113] [drm:dpu_plane_duplicate_state] plane51 [ 45.631119] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000060cca94c state to 00000000c7b1c2b4 [ 45.631129] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 0000000060cca94c [ 45.631136] [drm:dpu_plane_duplicate_state] plane57 [ 45.631142] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000023afd08c state to 00000000c7b1c2b4 [ 45.631152] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 0000000023afd08c [ 45.631160] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 00000000ecedc2d0 [ 45.631167] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 45.631172] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 45.631178] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 00000000c7b1c2b4 [ 45.631187] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.631192] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 45.631196] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000f8c6cdc2 state to 00000000c7b1c2b4 [ 45.631204] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.631209] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000f8c6cdc2 to [NOCRTC] [ 45.631217] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.631222] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000f8c6cdc2 to [CRTC:63:crtc-0] [ 45.631231] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 00000000c7b1c2b4 [ 45.631238] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 45.631243] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 45.631247] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 45.631252] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 45.631257] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 45.631262] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 45.631268] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 45.631274] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 45.631279] msm_dpu 1a01000.display-controller: [drm] layers: [ 45.631283] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 45.631289] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 45.631294] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 45.631299] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 45.631304] msm_dpu 1a01000.display-controller: [drm] name=0 [ 45.631309] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 45.631314] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 45.631319] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 45.631324] msm_dpu 1a01000.display-controller: [drm] imported=no [ 45.631328] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 45.631334] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 45.631342] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.631347] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.631352] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.631357] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.631361] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.631365] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 45.631369] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 45.631373] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.631378] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.631382] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 45.631388] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 45.631393] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 45.631398] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.631402] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.631406] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.631411] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.631418] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.631422] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.631426] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.631430] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.631434] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.631439] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.631443] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 45.631447] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.631451] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.631455] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.631460] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.631466] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 45.631470] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.631474] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.631478] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.631483] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.631489] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.631494] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.631498] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.631502] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.631506] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.631510] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.631514] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 45.631518] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.631522] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.631526] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.631531] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.631537] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 45.631541] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.631545] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.631549] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.631554] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.631560] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.631564] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.631568] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.631572] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.631576] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.631579] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.631584] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 45.631587] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.631591] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.631595] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.631600] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.631605] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 45.631610] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.631614] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.631618] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.631623] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.631629] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.631633] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.631637] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.631641] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.631645] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.631649] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.631654] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 45.631658] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.631662] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.631666] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.631671] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.631676] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 45.631680] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 45.631685] msm_dpu 1a01000.display-controller: [drm] active=1 [ 45.631689] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 45.631693] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 45.631697] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 45.631701] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 45.631705] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 45.631710] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.631714] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 45.631718] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 45.631722] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 45.631726] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 45.631736] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 45.631741] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 45.631746] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 45.631751] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 45.631755] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 45.631759] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 45.631763] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 45.631767] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 00000000c7b1c2b4 [ 45.631778] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 45.631788] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 45.631799] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 45.631809] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 00000000c97c760e to 00000000c7b1c2b4 [ 45.631817] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 45.631827] [drm:dpu_encoder_virt_atomic_check] enc31 [ 45.631834] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 00000000054c7d66 to 00000000c7b1c2b4 [ 45.631846] [drm:dpu_crtc_atomic_check] crtc63: check [ 45.631857] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 45.631867] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 45.631875] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 45.631887] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 00000000c7b1c2b4 [ 45.631896] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 45.631905] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 45.631918] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.631928] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,363)@ 45.625762 -> 45.622643 [e 9 us, 0 rep] [ 45.631948] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.631956] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,367)@ 45.625791 -> 45.622638 [e 8 us, 0 rep] [ 45.631973] DPU:KMS: dpu_kms_enable_commit [ 45.631976] DPU:KMS: dpu_kms_wait_flush [ 45.631978] DPU:KMS: dpu_kms_wait_for_commit_done [ 45.631980] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 45.631987] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.631995] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.662318] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 45.662473] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:45656161284 [ 45.686336] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.686348] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.686357] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 45.686362] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 45.686369] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 45.686382] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 45.686394] [drm:dpu_crtc_atomic_begin] crtc63 [ 45.686403] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.686411] [drm:_dpu_crtc_blend_setup] crtc63 [ 45.686420] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 45.686429] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 45.686438] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 45.686446] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 45.686454] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 45.686462] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 45.686469] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 45.686478] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 45.686486] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 45.686495] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 45.686507] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 45.686515] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 45.686523] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 45.686531] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 45.686543] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 45.686551] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 45.686559] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 45.686567] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 45.686575] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 45.686582] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 45.686592] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 45.686600] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 45.686608] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 45.686616] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 45.686625] [drm:dpu_plane_atomic_update] plane33 [ 45.686631] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 45.686646] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 45.686655] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 45.686663] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 45.686671] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 45.686679] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 45.686687] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 45.686695] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 45.686703] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 45.686711] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 45.686719] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 45.686728] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 45.686736] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 45.686744] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 45.686752] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 45.686760] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 45.686768] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 45.686776] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 45.686784] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 45.686792] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 45.686800] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 45.686808] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 45.686815] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 45.686823] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 45.686832] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 45.686840] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 45.686848] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 45.686856] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 45.686864] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.686872] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 45.686879] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 45.686887] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 45.686896] [drm:dpu_crtc_atomic_flush] crtc63 [ 45.686905] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 45.686916] DPU:KMS: dpu_kms_flush_commit [ 45.686918] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.686927] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.686997] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687066] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687135] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687204] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687272] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687341] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687409] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687477] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687545] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687613] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687683] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687751] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687819] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687887] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.687955] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688023] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688091] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688159] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688228] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688296] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688364] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688432] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688500] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688568] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688636] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688704] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688774] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688842] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688910] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.688978] hw recovery is not complete for ctl:1 [ 45.688982] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 45.688991] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 45.688998] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 45.689003] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 45.689011] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 45.689019] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 45.689029] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.689036] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 45.689045] DPU:KMS: dpu_kms_wait_flush [ 45.689047] DPU:KMS: dpu_kms_wait_for_commit_done [ 45.689049] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 45.689055] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.689062] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.689308] DPU:KMS: mdp_snapshot: START [ 45.690243] DPU:KMS: mdp_snapshot: DONE [ 45.742334] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.742347] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.742355] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 45.742360] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 45.742366] DPU:KMS: dpu_kms_complete_comit [ 45.742368] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 45.742379] [drm:dpu_crtc_complete_commit] crtc63: send event: 000000000aff3ec0 [ 45.742389] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 45.742399] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 45.742407] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.742413] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 45.742418] [drm:dpu_crtc_destroy_state] crtc63 [ 45.742427] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 45.742433] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 45.742440] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 00000000c7b1c2b4 [ 45.742472] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 00000000c7b1c2b4 [ 45.742480] [drm:dpu_plane_duplicate_state] plane33 [ 45.742485] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 45.742490] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000d05cc508 state to 00000000c7b1c2b4 [ 45.742503] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 45.742508] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000005f998769 state to 00000000c7b1c2b4 [ 45.742519] [drm:dpu_plane_duplicate_state] plane39 [ 45.742525] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000000e620d3d state to 00000000c7b1c2b4 [ 45.742537] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 000000000e620d3d [ 45.742544] [drm:dpu_plane_duplicate_state] plane45 [ 45.742550] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000002b5375e3 state to 00000000c7b1c2b4 [ 45.742561] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 000000002b5375e3 [ 45.742567] [drm:dpu_plane_duplicate_state] plane51 [ 45.742573] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000095ea3066 state to 00000000c7b1c2b4 [ 45.742586] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 0000000095ea3066 [ 45.742593] [drm:dpu_plane_duplicate_state] plane57 [ 45.742598] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000080770e55 state to 00000000c7b1c2b4 [ 45.742608] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 0000000080770e55 [ 45.742617] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 00000000d05cc508 [ 45.742624] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 45.742629] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 45.742635] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 45.742641] [drm:dpu_crtc_destroy_state] crtc63 [ 45.742649] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 45.742654] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 45.742824] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009bf3d1f9 [ 45.742836] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 45.742844] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000007027eac state to 000000009bf3d1f9 [ 45.742857] [drm:dpu_plane_duplicate_state] plane33 [ 45.742863] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 45.742870] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000077300e58 state to 000000009bf3d1f9 [ 45.742882] [drm:dpu_plane_duplicate_state] plane39 [ 45.742888] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000257f9ae7 state to 000000009bf3d1f9 [ 45.742899] [drm:dpu_plane_duplicate_state] plane45 [ 45.742905] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000dcf733d9 state to 000000009bf3d1f9 [ 45.742915] [drm:dpu_plane_duplicate_state] plane51 [ 45.742921] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 00000000df8c4384 state to 000000009bf3d1f9 [ 45.742931] [drm:dpu_plane_duplicate_state] plane57 [ 45.742937] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 000000008f52cf7b state to 000000009bf3d1f9 [ 45.742950] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.742955] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 45.742961] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000a36e9c41 state to 000000009bf3d1f9 [ 45.742979] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009bf3d1f9 [ 45.742986] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.742991] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 45.742996] [drm:dpu_crtc_destroy_state] crtc63 [ 45.743004] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 45.743009] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 45.743015] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009bf3d1f9 [ 45.743117] [drm:dpu_plane_duplicate_state] plane33 [ 45.743126] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 45.743134] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000080770e55 state to 00000000c7b1c2b4 [ 45.743148] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 45.743155] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000095ea3066 state to 00000000c7b1c2b4 [ 45.743167] [drm:dpu_plane_duplicate_state] plane39 [ 45.743174] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000002b5375e3 state to 00000000c7b1c2b4 [ 45.743185] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 000000002b5375e3 [ 45.743193] [drm:dpu_plane_duplicate_state] plane45 [ 45.743198] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000000e620d3d state to 00000000c7b1c2b4 [ 45.743209] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 000000000e620d3d [ 45.743217] [drm:dpu_plane_duplicate_state] plane51 [ 45.743222] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 00000000d05cc508 state to 00000000c7b1c2b4 [ 45.743234] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 00000000d05cc508 [ 45.743241] [drm:dpu_plane_duplicate_state] plane57 [ 45.743246] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 000000005f998769 state to 00000000c7b1c2b4 [ 45.743257] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 000000005f998769 [ 45.743265] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 0000000080770e55 [ 45.743272] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 45.743277] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 45.743283] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 00000000c7b1c2b4 [ 45.743292] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.743296] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 45.743301] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 000000001169e4eb state to 00000000c7b1c2b4 [ 45.743309] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.743314] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000001169e4eb to [NOCRTC] [ 45.743322] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.743327] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000001169e4eb to [CRTC:63:crtc-0] [ 45.743336] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 00000000c7b1c2b4 [ 45.743342] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 45.743347] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 45.743351] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 45.743356] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 45.743361] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 45.743366] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 45.743372] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 45.743378] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 45.743383] msm_dpu 1a01000.display-controller: [drm] layers: [ 45.743388] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 45.743393] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 45.743398] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 45.743403] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 45.743408] msm_dpu 1a01000.display-controller: [drm] name=0 [ 45.743412] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 45.743417] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 45.743423] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 45.743427] msm_dpu 1a01000.display-controller: [drm] imported=no [ 45.743432] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 45.743438] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 45.743446] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.743450] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.743454] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.743459] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.743463] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.743467] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 45.743472] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 45.743476] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.743480] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.743484] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 45.743490] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 45.743495] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 45.743501] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.743505] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.743509] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.743514] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.743520] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.743525] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.743529] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.743533] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.743538] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.743542] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.743546] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 45.743550] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.743554] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.743558] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.743563] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.743569] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 45.743573] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.743577] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.743582] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.743587] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.743593] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.743597] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.743601] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.743606] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.743610] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.743614] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.743618] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 45.743622] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.743626] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.743630] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.743635] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.743640] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 45.743645] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.743649] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.743653] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.743658] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.743664] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.743668] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.743672] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.743677] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.743681] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.743686] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.743690] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 45.743694] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.743698] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.743702] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.743707] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.743712] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 45.743717] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 45.743721] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 45.743725] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 45.743729] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 45.743736] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 45.743740] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 45.743744] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 45.743748] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 45.743752] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.743756] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 45.743761] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 45.743764] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 45.743768] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 45.743773] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 45.743777] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 45.743783] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 45.743787] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 45.743791] msm_dpu 1a01000.display-controller: [drm] active=1 [ 45.743795] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 45.743800] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 45.743804] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 45.743808] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 45.743812] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 45.743816] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 45.743821] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 45.743825] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 45.743829] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 45.743833] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 45.743843] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 45.743847] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 45.743852] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 45.743856] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 45.743861] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 45.743865] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 45.743869] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 45.743873] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 00000000c7b1c2b4 [ 45.743883] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 45.743893] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 45.743904] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 45.743913] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 0000000045e7a46d to 00000000c7b1c2b4 [ 45.743922] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 45.743931] [drm:dpu_encoder_virt_atomic_check] enc31 [ 45.743938] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 00000000295145bb to 00000000c7b1c2b4 [ 45.743948] [drm:dpu_crtc_atomic_check] crtc63: check [ 45.743958] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 45.743968] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 45.743975] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 45.743986] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 00000000c7b1c2b4 [ 45.743995] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 45.744004] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 45.744016] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.744026] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1771)@ 45.737861 -> 45.722646 [e 9 us, 0 rep] [ 45.744046] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.744055] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1774)@ 45.737889 -> 45.722649 [e 8 us, 0 rep] [ 45.744071] DPU:KMS: dpu_kms_enable_commit [ 45.744074] DPU:KMS: dpu_kms_wait_flush [ 45.744076] DPU:KMS: dpu_kms_wait_for_commit_done [ 45.744078] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 45.744084] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.744091] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.774319] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 45.774465] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:45768162170 [ 45.798326] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.798338] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.798348] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 45.798353] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 45.798360] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 45.798373] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 45.798385] [drm:dpu_crtc_atomic_begin] crtc63 [ 45.798395] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.798403] [drm:_dpu_crtc_blend_setup] crtc63 [ 45.798412] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 45.798422] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 45.798430] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 45.798438] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 45.798446] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 45.798454] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 45.798462] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 45.798470] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 45.798478] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 45.798487] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 45.798499] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 45.798507] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 45.798515] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 45.798523] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 45.798534] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 45.798542] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 45.798551] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 45.798559] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 45.798567] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 45.798574] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 45.798584] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 45.798592] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 45.798600] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 45.798608] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 45.798617] [drm:dpu_plane_atomic_update] plane33 [ 45.798624] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 45.798638] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 45.798647] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 45.798655] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 45.798663] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 45.798671] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 45.798679] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 45.798687] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 45.798695] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 45.798702] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 45.798710] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 45.798719] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 45.798727] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 45.798735] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 45.798743] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 45.798751] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 45.798759] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 45.798767] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 45.798775] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 45.798783] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 45.798791] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 45.798799] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 45.798807] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 45.798816] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 45.798824] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 45.798832] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 45.798840] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 45.798848] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 45.798856] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 45.798865] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 45.798872] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 45.798879] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 45.798888] [drm:dpu_crtc_atomic_flush] crtc63 [ 45.798896] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 45.798907] DPU:KMS: dpu_kms_flush_commit [ 45.798910] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.798918] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.798988] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799058] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799127] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799195] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799264] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799332] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799400] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799468] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799536] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799604] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799672] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799741] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799809] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799877] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.799945] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800013] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800081] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800150] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800218] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800287] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800355] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800423] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800491] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800559] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800627] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800695] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800763] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800832] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800900] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 45.800968] hw recovery is not complete for ctl:1 [ 45.800971] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 45.800980] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 45.800987] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 45.800992] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 45.801000] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 45.801008] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 45.801017] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.801024] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 45.801033] DPU:KMS: dpu_kms_wait_flush [ 45.801034] DPU:KMS: dpu_kms_wait_for_commit_done [ 45.801036] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 45.801042] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.801050] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.801298] DPU:KMS: mdp_snapshot: START [ 45.802235] DPU:KMS: mdp_snapshot: DONE [ 45.854335] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.854348] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 45.854356] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 45.854361] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 45.854366] DPU:KMS: dpu_kms_complete_comit [ 45.854368] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 45.854379] [drm:dpu_crtc_complete_commit] crtc63: send event: 000000000aff3ec0 [ 45.854389] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 45.854399] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 45.854408] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.854414] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 45.854419] [drm:dpu_crtc_destroy_state] crtc63 [ 45.854428] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 45.854433] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 45.854440] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 00000000c7b1c2b4 [ 45.854588] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009bf3d1f9 [ 45.854599] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 45.854607] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000008f52cf7b state to 000000009bf3d1f9 [ 45.854621] [drm:dpu_plane_duplicate_state] plane33 [ 45.854627] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 45.854633] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000df8c4384 state to 000000009bf3d1f9 [ 45.854645] [drm:dpu_plane_duplicate_state] plane39 [ 45.854650] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000dcf733d9 state to 000000009bf3d1f9 [ 45.854662] [drm:dpu_plane_duplicate_state] plane45 [ 45.854667] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000257f9ae7 state to 000000009bf3d1f9 [ 45.854678] [drm:dpu_plane_duplicate_state] plane51 [ 45.854683] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000077300e58 state to 000000009bf3d1f9 [ 45.854694] [drm:dpu_plane_duplicate_state] plane57 [ 45.854699] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000007027eac state to 000000009bf3d1f9 [ 45.854711] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 45.854716] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 45.854722] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000a402007c state to 000000009bf3d1f9 [ 45.854736] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009bf3d1f9 [ 45.854743] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 45.854748] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 45.854753] [drm:dpu_crtc_destroy_state] crtc63 [ 45.854762] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 45.854767] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 45.854773] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009bf3d1f9 [ 45.886449] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 45.886632] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:45880301388 [ 46.018497] cpu cpu4: _set_opp: switching OPP: Freq 1190400000 -> 400000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 46.396254] cpu cpu0: _set_opp: switching OPP: Freq 1401600000 -> 200000000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 46.562797] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 00000000968f3705 [ 46.562898] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 46.562959] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000003dab1ac0 state to 00000000968f3705 [ 46.563060] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 00000000968f3705 [ 46.563135] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 46.563179] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 46.563226] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 0000000020814213 state to 00000000968f3705 [ 46.563300] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000968f3705 [ 46.563356] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 46.563403] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 46.563447] [drm:dpu_crtc_destroy_state] crtc63 [ 46.563513] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 46.563565] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 00000000968f3705 [ 48.574050] [drm:drm_stub_open] [ 48.574154] msm_dpu 1a01000.display-controller: [drm:drm_open_helper] comm="elogind", pid=3821, minor=0 [ 48.574443] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="elogind" pid=3821, dev=0xe200, auth=1, DRM_IOCTL_SET_MASTER [ 48.577622] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES [ 48.582375] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_VERSION [ 48.582534] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_VERSION [ 48.582796] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 48.582906] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 48.583004] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 48.583103] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_SET_CLIENT_CAP [ 48.583199] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 48.583301] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_SET_CLIENT_CAP [ 48.583442] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 48.583548] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 48.583691] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES [ 48.583814] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES [ 48.583981] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCRTC [ 48.584111] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.584240] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.584375] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.584483] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.584600] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.584699] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.584805] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.584906] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.585012] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.585113] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.585229] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES [ 48.585338] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES [ 48.585495] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 48.585613] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 48.585736] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.585864] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.586008] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.586118] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.586319] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.586433] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.586543] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.586646] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.586757] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.586857] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.586965] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.587065] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.587173] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.587273] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.587380] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.587481] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.587590] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.587690] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.587797] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.587897] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.588006] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.588106] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.588214] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.588314] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.588420] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.588521] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.588627] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.588725] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.588828] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.588927] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.589035] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.589135] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.589242] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.589349] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.589466] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.589574] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.589700] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.589800] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.589913] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.590036] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.590536] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.590672] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.590821] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 48.590912] [drm:drm_mode_object_put.part.0] OBJ ID: 34 (2) [ 48.590982] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 48.591070] [drm:drm_mode_object_put.part.0] OBJ ID: 34 (2) [ 48.591255] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 48.591366] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 48.591488] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.591609] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.591750] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.591857] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.591977] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.592081] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.592188] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.592289] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.592397] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.592498] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.592604] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.592705] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.592811] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.592913] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.593022] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.593124] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.593231] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.593331] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.593440] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.593541] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.593650] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.593751] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.593859] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.593959] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.594066] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.594236] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.594366] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.594468] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.594574] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.594674] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.594784] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.594885] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.594995] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.595101] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.595219] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.595326] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.595454] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.595556] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.595669] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.595794] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.595945] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 48.596056] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 48.596175] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.596293] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.596433] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.596540] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.596658] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.596762] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.596870] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.596971] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.597080] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.597180] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.597286] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.597385] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.597492] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.597592] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.597699] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.597800] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.597907] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.598006] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.598114] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.598280] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.598398] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.598502] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.598611] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.598712] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.598819] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.598919] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.599027] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.599125] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.599229] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.599329] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.599437] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.599537] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.599643] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.599747] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.599864] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.599971] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.600096] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.600197] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.600307] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.600428] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.600576] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 48.600687] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 48.600805] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.600923] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.601062] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.601169] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.601287] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.601389] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.601497] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.601597] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.601703] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.601802] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.601910] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.602011] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.602117] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.602274] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.602390] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.602492] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.602602] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.602704] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.602812] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.602912] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.603020] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.603120] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.603227] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.603328] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.603435] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.603535] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.603645] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.603743] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.603846] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.603946] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.604054] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.604153] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.604259] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.604364] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.604482] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.604590] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.604715] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.604814] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.604926] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.605048] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.605194] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 48.605303] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 48.605420] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.605538] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.605677] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.605784] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.605899] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.605999] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.606108] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.606290] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.606407] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.606510] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.606617] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.606717] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.606823] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.606922] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.607029] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.607129] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.607237] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.607337] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.607444] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.607543] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.607650] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.607749] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.607855] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.607954] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.608063] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.608162] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.608268] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.608366] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.608470] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.608569] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.608675] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.608774] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.608881] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.608985] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.609103] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.609210] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.609335] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.609435] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 48.609546] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.609668] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.609920] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.610044] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 48.610258] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 48.610355] [drm:drm_mode_object_put.part.0] OBJ ID: 58 (2) [ 48.610429] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 48.610516] [drm:drm_mode_object_put.part.0] OBJ ID: 58 (2) [ 48.624983] [drm:drm_stub_open] [ 48.625086] msm_dpu 1a01000.display-controller: [drm:drm_open_helper] comm="phoc", pid=4387, minor=128 [ 48.625244] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 48.625364] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 48.672317] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 48.672473] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 49.217887] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 49.217964] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 49.232409] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 49.232475] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 49.233020] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 49.233071] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 49.233166] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, MSM_GEM_NEW [ 49.233205] msm_dpu 1a01000.display-controller: [drm:msm_gem_new_impl.isra.0] invalid cache flag: 80000 [ 49.233240] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4387, ret=-22 [ 49.233368] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, MSM_GET_PARAM [ 49.233404] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4387, ret=-6 [ 49.233526] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, MSM_GET_PARAM [ 49.233562] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4387, ret=-6 [ 49.233621] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, MSM_GET_PARAM [ 49.233654] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4387, ret=-6 [ 49.233708] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4387, dev=0xe280, auth=0, MSM_GET_PARAM [ 49.233741] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4387, ret=-6 [ 49.264086] msm_dpu 1a01000.display-controller: [drm:drm_release] open_count = 2 [ 49.264137] msm_dpu 1a01000.display-controller: [drm:drm_file_free] comm="phoc", pid=4387, dev=0xe280, open_count=2 [ 49.268855] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="elogind" pid=3821, dev=0xe200, auth=1, DRM_IOCTL_DROP_MASTER [ 49.268943] msm_dpu 1a01000.display-controller: [drm:drm_release] open_count = 1 [ 49.268971] msm_dpu 1a01000.display-controller: [drm:drm_file_free] comm="elogind", pid=3821, dev=0xe200, open_count=1 [ 49.269008] msm_dpu 1a01000.display-controller: [drm:_drm_lease_revoke] revoke leases for 000000000989070c 0 [ 49.269042] msm_dpu 1a01000.display-controller: [drm:drm_lease_destroy] drm_lease_destroy 0 [ 49.269070] msm_dpu 1a01000.display-controller: [drm:drm_lease_destroy] drm_lease_destroy done 0 [ 49.269106] msm_dpu 1a01000.display-controller: [drm:drm_lastclose] [ 49.269128] msm_dpu 1a01000.display-controller: [drm:drm_lastclose] driver lastclose completed [ 49.269160] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 00000000c7b1c2b4 [ 49.269190] [drm:dpu_plane_duplicate_state] plane33 [ 49.269216] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 49.269237] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000a6fd7584 state to 00000000c7b1c2b4 [ 49.269282] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 49.269300] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000006f973e3b state to 00000000c7b1c2b4 [ 49.269336] [drm:dpu_plane_duplicate_state] plane39 [ 49.269355] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000007793f104 state to 00000000c7b1c2b4 [ 49.269389] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 000000007793f104 [ 49.269413] [drm:dpu_plane_duplicate_state] plane45 [ 49.269431] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000a00411f6 state to 00000000c7b1c2b4 [ 49.269465] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 00000000a00411f6 [ 49.269488] [drm:dpu_plane_duplicate_state] plane51 [ 49.269505] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 000000008b1dc0e8 state to 00000000c7b1c2b4 [ 49.269538] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 000000008b1dc0e8 [ 49.269567] [drm:dpu_plane_duplicate_state] plane57 [ 49.269587] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 00000000f41262b9 state to 00000000c7b1c2b4 [ 49.269620] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 00000000f41262b9 [ 49.269649] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 00000000a6fd7584 [ 49.269671] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 49.269686] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 49.269706] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 00000000c7b1c2b4 [ 49.269736] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.269751] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 49.269767] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000054c7d66 state to 00000000c7b1c2b4 [ 49.269792] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.269809] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000054c7d66 to [NOCRTC] [ 49.269834] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.269850] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000054c7d66 to [CRTC:63:crtc-0] [ 49.269876] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 00000000c7b1c2b4 [ 49.269897] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 49.269914] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 49.269927] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 49.269941] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 49.269958] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 49.269974] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 49.269993] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 49.270008] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 49.270025] msm_dpu 1a01000.display-controller: [drm] layers: [ 49.270038] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 49.270055] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 49.270071] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 49.270086] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 49.270101] msm_dpu 1a01000.display-controller: [drm] name=0 [ 49.270115] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 49.270129] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 49.270145] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 49.270161] msm_dpu 1a01000.display-controller: [drm] imported=no [ 49.270314] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 49.270337] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 49.270362] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.270376] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.270390] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.270404] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.270418] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.270433] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 49.270446] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 49.270460] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.270474] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.270487] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 49.270504] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 49.270522] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 49.270536] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.270549] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.270563] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.270579] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.270601] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.270614] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.270628] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.270641] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.270655] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.270669] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.270682] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 49.270695] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.270708] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.270721] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.270736] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.270752] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 49.270766] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.270779] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.270792] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.270808] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.270828] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.270842] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.270855] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.270868] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.270882] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.270896] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.270909] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 49.270923] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.270936] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.270948] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.270964] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.270980] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 49.270993] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.271006] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.271019] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.271034] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.271054] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.271068] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.271081] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.271094] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.271107] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.271122] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.271135] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 49.271149] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.271162] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.271175] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.271191] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.271206] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 49.271220] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.271233] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.271246] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.271262] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.271282] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.271295] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.271308] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.271321] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.271334] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.271348] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.271361] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 49.271374] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.271387] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.271400] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.271416] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.271432] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 49.271446] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 49.271459] msm_dpu 1a01000.display-controller: [drm] active=1 [ 49.271472] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 49.271485] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 49.271499] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 49.271512] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 49.271525] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 49.271538] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.271551] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 49.271565] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 49.271578] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 49.271592] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 49.271622] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 49.271637] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 49.271652] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 49.271667] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 49.271680] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 49.271694] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 49.271707] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 49.271722] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 00000000c7b1c2b4 [ 49.271758] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 49.271795] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 49.271827] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 49.271856] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 00000000eb476a6e to 00000000c7b1c2b4 [ 49.271882] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 49.271910] [drm:dpu_encoder_virt_atomic_check] enc31 [ 49.271935] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 000000008402c5ae to 00000000c7b1c2b4 [ 49.271974] [drm:dpu_crtc_atomic_check] crtc63: check [ 49.272005] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 49.272037] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 49.272061] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 49.272093] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 00000000c7b1c2b4 [ 49.272118] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 49.272146] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 49.272185] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.272215] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.272240] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.272265] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0: Noisy timestamp 23 us > 20 us [3 reps]. [ 49.272308] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1153)@ 49.266098 -> 49.256192 [e 23 us, 3 rep] [ 49.272359] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.272384] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.272409] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.272434] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0: Noisy timestamp 23 us > 20 us [3 reps]. [ 49.272473] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1173)@ 49.266266 -> 49.256189 [e 23 us, 3 rep] [ 49.272524] DPU:KMS: dpu_kms_enable_commit [ 49.272533] DPU:KMS: dpu_kms_wait_flush [ 49.272542] DPU:KMS: dpu_kms_wait_for_commit_done [ 49.272550] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 49.272572] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.272595] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.326696] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.326754] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.326780] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 49.326800] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 49.326825] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 49.326868] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 49.326904] [drm:dpu_crtc_atomic_begin] crtc63 [ 49.326934] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.326959] [drm:_dpu_crtc_blend_setup] crtc63 [ 49.326986] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 49.327015] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 49.327040] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 49.327065] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 49.327090] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 49.327114] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 49.327137] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 49.327162] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 49.327186] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 49.327212] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 49.327247] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 49.327274] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 49.327298] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 49.327323] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 49.327359] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 49.327383] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 49.327410] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 49.327435] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 49.327457] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 49.327483] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 49.327511] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 49.327536] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 49.327561] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 49.327584] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 49.327610] [drm:dpu_plane_atomic_update] plane33 [ 49.327632] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 49.327674] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 49.327702] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 49.327728] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 49.327752] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 49.327777] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 49.327802] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 49.327826] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 49.327852] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 49.327876] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 49.327900] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 49.327927] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 49.327952] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 49.327976] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 49.328001] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 49.328026] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 49.328050] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 49.328075] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 49.328099] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 49.328123] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 49.328148] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 49.328171] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 49.328194] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 49.328221] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 49.328246] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 49.328271] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 49.328297] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 49.328319] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 49.328346] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.328370] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 49.328392] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 49.328415] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 49.328444] [drm:dpu_crtc_atomic_flush] crtc63 [ 49.328470] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 49.328505] DPU:KMS: dpu_kms_flush_commit [ 49.328515] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.328540] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.328647] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.328749] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.328849] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.328947] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.329045] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.329142] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.329239] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.329336] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.329435] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.329534] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.329630] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.329728] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.329824] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.329920] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.330018] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.330115] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.330217] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.330319] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.330417] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.330515] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.330616] hw recovery is not complete for ctl:1 [ 49.330630] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 49.330663] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 49.330686] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 49.330702] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 49.330725] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 49.330748] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 49.330780] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.330802] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 49.330830] DPU:KMS: dpu_kms_wait_flush [ 49.330837] DPU:KMS: dpu_kms_wait_for_commit_done [ 49.330845] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 49.330865] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.330889] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.331475] DPU:KMS: mdp_snapshot: START [ 49.332587] DPU:KMS: mdp_snapshot: DONE [ 49.386997] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.387059] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.387086] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 49.387105] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 49.387123] DPU:KMS: dpu_kms_complete_comit [ 49.387131] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 49.387168] [drm:dpu_crtc_complete_commit] crtc63: send event: 000000000aff3ec0 [ 49.387203] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 49.387240] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 49.387268] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.387290] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 49.387307] [drm:dpu_crtc_destroy_state] crtc63 [ 49.387334] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 49.387353] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 49.387380] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 00000000c7b1c2b4 [ 49.387422] msm_dpu 1a01000.display-controller: [drm:drm_client_dev_restore] fbdev: ret=0 [ 49.387675] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009958c70e [ 49.387716] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 49.387741] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000016c42f3f state to 000000009958c70e [ 49.387784] [drm:dpu_plane_duplicate_state] plane33 [ 49.387805] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 49.387823] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000081dd1a9d state to 000000009958c70e [ 49.387861] [drm:dpu_plane_duplicate_state] plane39 [ 49.387881] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000004c5d1e92 state to 000000009958c70e [ 49.387916] [drm:dpu_plane_duplicate_state] plane45 [ 49.387935] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000afe6e5c7 state to 000000009958c70e [ 49.387969] [drm:dpu_plane_duplicate_state] plane51 [ 49.387986] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000098756489 state to 000000009958c70e [ 49.388021] [drm:dpu_plane_duplicate_state] plane57 [ 49.388039] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000029eeaabd state to 000000009958c70e [ 49.388062] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 00000000c7b1c2b4 [ 49.388075] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.388091] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 49.388106] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000c88fa867 state to 000000009958c70e [ 49.388134] [drm:dpu_plane_duplicate_state] plane33 [ 49.388155] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 49.388161] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009958c70e [ 49.388181] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.388173] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000008f220f7 state to 00000000c7b1c2b4 [ 49.388197] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 49.388214] [drm:drm_mode_object_get] OBJ ID: 65 (3) [ 49.388212] [drm:dpu_crtc_destroy_state] crtc63 [ 49.388231] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000004e3db5bb state to 00000000c7b1c2b4 [ 49.388239] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (4) [ 49.388255] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 49.388264] [drm:dpu_plane_duplicate_state] plane39 [ 49.388273] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009958c70e [ 49.388283] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000001be180a9 state to 00000000c7b1c2b4 [ 49.388317] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 000000001be180a9 [ 49.388338] [drm:dpu_plane_duplicate_state] plane45 [ 49.388354] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000eb55b7ca state to 00000000c7b1c2b4 [ 49.388386] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 00000000eb55b7ca [ 49.388406] [drm:dpu_plane_duplicate_state] plane51 [ 49.388422] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 00000000126e7d46 state to 00000000c7b1c2b4 [ 49.388453] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 00000000126e7d46 [ 49.388473] [drm:dpu_plane_duplicate_state] plane57 [ 49.388488] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000044538543 state to 00000000c7b1c2b4 [ 49.388520] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 0000000044538543 [ 49.388545] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 0000000008f220f7 [ 49.388566] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 49.388579] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 49.388597] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 00000000c7b1c2b4 [ 49.388622] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.388635] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 49.388649] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000295145bb state to 00000000c7b1c2b4 [ 49.388672] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.388687] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000295145bb to [NOCRTC] [ 49.388709] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.388723] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000295145bb to [CRTC:63:crtc-0] [ 49.388747] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 00000000c7b1c2b4 [ 49.388766] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 49.388781] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 49.388792] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 49.388804] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 49.388820] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 49.388834] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 49.388853] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 49.388868] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 49.388883] msm_dpu 1a01000.display-controller: [drm] layers: [ 49.388895] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 49.388911] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 49.388924] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 49.388937] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 49.388951] msm_dpu 1a01000.display-controller: [drm] name=0 [ 49.388963] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 49.388976] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 49.388990] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 49.389004] msm_dpu 1a01000.display-controller: [drm] imported=no [ 49.389017] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 49.389034] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 49.389056] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.389067] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.389080] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.389092] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.389104] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.389116] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 49.389128] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 49.389139] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.389151] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.389162] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 49.389177] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 49.389192] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 49.389205] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.389217] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.389228] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.389242] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.389261] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.389273] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.389284] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.389295] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.389307] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.389318] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.389330] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 49.389341] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.389352] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.389363] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.389377] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.389391] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 49.389404] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.389416] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.389427] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.389440] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.389459] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.389470] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.389481] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.389493] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.389505] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.389517] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.389529] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 49.389540] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.389551] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.389562] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.389575] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.389589] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 49.389602] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.389613] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.389624] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.389637] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.389655] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.389666] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.389678] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.389689] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.389701] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.389713] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.389724] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 49.389736] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.389747] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.389758] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.389772] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.389785] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 49.389798] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.389809] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.389820] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.389834] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.389851] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.389863] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.389874] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.389885] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.389897] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.389908] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.389920] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 49.389931] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.389942] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.389954] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.389967] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.389982] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 49.389994] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 49.390006] msm_dpu 1a01000.display-controller: [drm] active=1 [ 49.390017] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 49.390029] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 49.390040] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 49.390052] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 49.390063] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 49.390075] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.390087] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 49.390098] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 49.390110] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 49.390122] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 49.390149] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 49.390163] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 49.390236] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 49.390251] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 49.390262] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 49.390275] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 49.390287] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 49.390300] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 00000000c7b1c2b4 [ 49.390331] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 49.390361] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 49.390391] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 49.390419] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 000000009d6a8861 to 00000000c7b1c2b4 [ 49.390442] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 49.390467] [drm:dpu_encoder_virt_atomic_check] enc31 [ 49.390487] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 00000000011b5ad1 to 00000000c7b1c2b4 [ 49.390520] [drm:dpu_crtc_atomic_check] crtc63: check [ 49.390549] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 49.390578] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 49.390600] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 49.390630] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 00000000c7b1c2b4 [ 49.390654] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 49.390681] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 49.390720] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.390746] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.390769] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.390791] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0: Noisy timestamp 20 us > 20 us [3 reps]. [ 49.390836] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1369)@ 49.384624 -> 49.372863 [e 20 us, 3 rep] [ 49.390886] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.390909] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.390931] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.390955] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0: Noisy timestamp 21 us > 20 us [3 reps]. [ 49.390990] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1388)@ 49.384787 -> 49.372863 [e 21 us, 3 rep] [ 49.391037] DPU:KMS: dpu_kms_enable_commit [ 49.391044] DPU:KMS: dpu_kms_wait_flush [ 49.391050] DPU:KMS: dpu_kms_wait_for_commit_done [ 49.391055] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 49.391074] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.391097] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.422409] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 49.422661] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:49416275502 [ 49.450775] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.450830] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.450857] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 49.450874] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 49.450897] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 49.450942] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 49.450976] [drm:dpu_crtc_atomic_begin] crtc63 [ 49.451004] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.451027] [drm:_dpu_crtc_blend_setup] crtc63 [ 49.451053] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 49.451078] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 49.451102] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 49.451125] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 49.451149] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 49.451171] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 49.451193] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 49.451215] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 49.451237] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 49.451263] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 49.451296] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 49.451321] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 49.451343] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 49.451366] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 49.451400] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 49.451421] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 49.451445] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 49.451468] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 49.451489] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 49.451512] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 49.451539] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 49.451562] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 49.451584] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 49.451606] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 49.451629] [drm:dpu_plane_atomic_update] plane33 [ 49.451648] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 49.451689] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 49.451714] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 49.451737] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 49.451759] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 49.451782] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 49.451804] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 49.451826] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 49.451849] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 49.451871] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 49.451893] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 49.451919] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 49.451942] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 49.451964] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 49.451987] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 49.452009] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 49.452031] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 49.452054] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 49.452076] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 49.452098] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 49.452122] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 49.452143] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 49.452164] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 49.452188] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 49.452211] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 49.452233] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 49.452258] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 49.452279] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 49.452303] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.452325] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 49.452345] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 49.452366] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 49.452391] [drm:dpu_crtc_atomic_flush] crtc63 [ 49.452416] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 49.452449] DPU:KMS: dpu_kms_flush_commit [ 49.452458] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.452481] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.452587] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.452690] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.452790] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.452889] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.452989] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.453089] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.453188] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.453289] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.453388] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.453487] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.453585] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.453684] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.453782] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.453881] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.453980] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.454079] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.454185] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.454286] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.454385] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.454487] hw recovery is not complete for ctl:1 [ 49.454497] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 49.454526] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 49.454547] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 49.454564] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 49.454586] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 49.454607] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 49.454635] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.454655] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 49.454682] DPU:KMS: dpu_kms_wait_flush [ 49.454687] DPU:KMS: dpu_kms_wait_for_commit_done [ 49.454694] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 49.454712] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.454734] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.454853] DPU:KMS: mdp_snapshot: START [ 49.455932] DPU:KMS: mdp_snapshot: DONE [ 49.514730] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.514786] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.514810] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 49.514829] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 49.514846] DPU:KMS: dpu_kms_complete_comit [ 49.514853] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 49.514886] [drm:dpu_crtc_complete_commit] crtc63: send event: 000000000aff3ec0 [ 49.514916] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 49.514949] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 49.514975] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.514994] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 49.515009] [drm:dpu_crtc_destroy_state] crtc63 [ 49.515033] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 49.515048] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 49.515069] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 00000000c7b1c2b4 [ 49.515107] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 00000000c7b1c2b4 [ 49.515128] [drm:dpu_plane_duplicate_state] plane33 [ 49.515145] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 49.515160] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000f41262b9 state to 00000000c7b1c2b4 [ 49.515197] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 49.515212] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000008b1dc0e8 state to 00000000c7b1c2b4 [ 49.515244] [drm:dpu_plane_duplicate_state] plane39 [ 49.515260] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000a00411f6 state to 00000000c7b1c2b4 [ 49.515292] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 00000000a00411f6 [ 49.515314] [drm:dpu_plane_duplicate_state] plane45 [ 49.515329] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000007793f104 state to 00000000c7b1c2b4 [ 49.515360] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 000000007793f104 [ 49.515380] [drm:dpu_plane_duplicate_state] plane51 [ 49.515396] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 00000000a6fd7584 state to 00000000c7b1c2b4 [ 49.515428] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 00000000a6fd7584 [ 49.515449] [drm:dpu_plane_duplicate_state] plane57 [ 49.515465] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 000000006f973e3b state to 00000000c7b1c2b4 [ 49.515496] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 000000006f973e3b [ 49.515520] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 00000000f41262b9 [ 49.515540] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 49.515554] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 49.515572] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 00000000c7b1c2b4 [ 49.515598] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.515611] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 49.515625] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 000000008402c5ae state to 00000000c7b1c2b4 [ 49.515648] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.515663] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000008402c5ae to [NOCRTC] [ 49.515685] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.515700] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000008402c5ae to [CRTC:63:crtc-0] [ 49.515724] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 00000000c7b1c2b4 [ 49.515743] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 49.515758] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 49.515769] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 49.515782] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 49.515798] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 49.515813] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 49.515832] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 49.515846] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 49.515861] msm_dpu 1a01000.display-controller: [drm] layers: [ 49.515873] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 49.515889] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 49.515903] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 49.515916] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 49.515931] msm_dpu 1a01000.display-controller: [drm] name=0 [ 49.515945] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 49.515957] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 49.515972] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 49.515986] msm_dpu 1a01000.display-controller: [drm] imported=no [ 49.516000] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 49.516017] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 49.516041] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.516054] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.516068] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.516080] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.516093] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.516106] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 49.516119] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 49.516131] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.516144] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.516156] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 49.516172] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 49.516188] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 49.516202] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.516213] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.516225] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.516240] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.516259] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.516272] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.516284] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.516296] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.516308] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.516320] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.516333] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 49.516344] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.516356] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.516368] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.516382] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.516397] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 49.516410] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.516421] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.516433] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.516447] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.516466] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.516478] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.516490] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.516502] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.516514] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.516526] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.516538] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 49.516550] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.516561] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.516573] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.516588] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.516602] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 49.516614] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.516626] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.516637] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.516652] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.516670] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.516682] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.516694] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.516706] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.516718] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.516730] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.516742] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 49.516754] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.516766] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.516777] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.516792] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.516806] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 49.516819] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.516830] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.516841] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.516856] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.516874] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.516886] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.516898] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.516910] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.516922] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.516934] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.516946] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 49.516958] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.516969] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.516981] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.516996] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.517010] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 49.517023] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 49.517035] msm_dpu 1a01000.display-controller: [drm] active=1 [ 49.517047] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 49.517059] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 49.517071] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 49.517083] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 49.517095] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 49.517107] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.517119] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 49.517131] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 49.517144] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 49.517156] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 49.517184] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 49.517198] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 49.517211] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 49.517224] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 49.517235] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 49.517248] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 49.517260] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 49.517273] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 00000000c7b1c2b4 [ 49.517302] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 49.517338] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 49.517369] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 49.517396] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 000000001bd118ab to 00000000c7b1c2b4 [ 49.517419] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 49.517445] [drm:dpu_encoder_virt_atomic_check] enc31 [ 49.517466] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 00000000f8c6cdc2 to 00000000c7b1c2b4 [ 49.517500] [drm:dpu_crtc_atomic_check] crtc63: check [ 49.517530] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 49.517560] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 49.517583] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 49.517614] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 00000000c7b1c2b4 [ 49.517637] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 49.517662] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 49.517699] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.517725] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.517748] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.517771] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0: Noisy timestamp 21 us > 20 us [3 reps]. [ 49.517814] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,628)@ 49.511604 -> 49.506209 [e 21 us, 3 rep] [ 49.517863] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.517886] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.517908] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.517931] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0: Noisy timestamp 21 us > 20 us [3 reps]. [ 49.517965] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,647)@ 49.511763 -> 49.506205 [e 21 us, 3 rep] [ 49.518011] DPU:KMS: dpu_kms_enable_commit [ 49.518019] DPU:KMS: dpu_kms_wait_flush [ 49.518025] DPU:KMS: dpu_kms_wait_for_commit_done [ 49.518031] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 49.518049] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.518072] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.546518] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 49.547153] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:49540408366 [ 49.574555] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.574599] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.574624] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 49.574641] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 49.574662] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 49.574704] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 49.574738] [drm:dpu_crtc_atomic_begin] crtc63 [ 49.574766] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.574789] [drm:_dpu_crtc_blend_setup] crtc63 [ 49.574815] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 49.574841] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 49.574865] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 49.574888] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 49.574910] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 49.574932] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 49.574954] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 49.574976] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 49.574999] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 49.575023] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 49.575057] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 49.575081] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 49.575104] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 49.575127] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 49.575161] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 49.575184] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 49.575208] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 49.575230] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 49.575251] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 49.575274] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 49.575302] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 49.575324] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 49.575347] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 49.575369] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 49.575392] [drm:dpu_plane_atomic_update] plane33 [ 49.575411] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 49.575453] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 49.575478] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 49.575501] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 49.575524] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 49.575546] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 49.575569] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 49.575592] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 49.575615] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 49.575638] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 49.575660] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 49.575686] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 49.575709] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 49.575731] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 49.575754] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 49.575776] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 49.575799] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 49.575822] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 49.575844] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 49.575866] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 49.575890] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 49.575912] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 49.575933] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 49.575957] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 49.575980] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 49.576002] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 49.576027] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 49.576048] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 49.576071] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.576093] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 49.576113] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 49.576134] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 49.576160] [drm:dpu_crtc_atomic_flush] crtc63 [ 49.576185] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 49.576217] DPU:KMS: dpu_kms_flush_commit [ 49.576225] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.576248] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.576353] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.576456] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.576556] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.576655] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.576757] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.576855] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.576954] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.577053] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.577152] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.577251] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.577350] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.577449] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.577548] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.577646] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.577745] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.577844] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.577946] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.578044] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.578143] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.578285] hw recovery is not complete for ctl:1 [ 49.578297] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 49.578318] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 49.578338] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 49.578352] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 49.578376] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 49.578397] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 49.578425] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.578446] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 49.578472] DPU:KMS: dpu_kms_wait_flush [ 49.578478] DPU:KMS: dpu_kms_wait_for_commit_done [ 49.578484] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 49.578502] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.578523] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.638475] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.638531] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.638556] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 49.638576] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 49.638591] DPU:KMS: dpu_kms_complete_comit [ 49.638598] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 49.638632] [drm:dpu_crtc_complete_commit] crtc63: send event: 000000000aff3ec0 [ 49.638663] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 49.638697] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 49.638723] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.638742] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 49.638757] [drm:dpu_crtc_destroy_state] crtc63 [ 49.638781] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 49.638797] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 49.638818] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 00000000c7b1c2b4 [ 49.638899] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 00000000c7b1c2b4 [ 49.638921] [drm:dpu_plane_duplicate_state] plane33 [ 49.638939] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 49.638954] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000044538543 state to 00000000c7b1c2b4 [ 49.638991] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 49.639006] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 00000000126e7d46 state to 00000000c7b1c2b4 [ 49.639039] [drm:dpu_plane_duplicate_state] plane39 [ 49.639056] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000eb55b7ca state to 00000000c7b1c2b4 [ 49.639088] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 00000000eb55b7ca [ 49.639109] [drm:dpu_plane_duplicate_state] plane45 [ 49.639125] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000001be180a9 state to 00000000c7b1c2b4 [ 49.639159] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 000000001be180a9 [ 49.639179] [drm:dpu_plane_duplicate_state] plane51 [ 49.639194] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000008f220f7 state to 00000000c7b1c2b4 [ 49.639226] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 0000000008f220f7 [ 49.639246] [drm:dpu_plane_duplicate_state] plane57 [ 49.639262] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 000000004e3db5bb state to 00000000c7b1c2b4 [ 49.639294] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 000000004e3db5bb [ 49.639318] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 0000000044538543 [ 49.639338] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 49.639351] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 49.639369] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 49.639386] [drm:dpu_crtc_destroy_state] crtc63 [ 49.639410] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 49.639424] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 49.639696] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009958c70e [ 49.639729] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 49.639752] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000029eeaabd state to 000000009958c70e [ 49.639791] [drm:dpu_plane_duplicate_state] plane33 [ 49.639809] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 49.639826] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000098756489 state to 000000009958c70e [ 49.639861] [drm:dpu_plane_duplicate_state] plane39 [ 49.639877] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000afe6e5c7 state to 000000009958c70e [ 49.639909] [drm:dpu_plane_duplicate_state] plane45 [ 49.639925] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000004c5d1e92 state to 000000009958c70e [ 49.639957] [drm:dpu_plane_duplicate_state] plane51 [ 49.639973] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000081dd1a9d state to 000000009958c70e [ 49.640004] [drm:dpu_plane_duplicate_state] plane57 [ 49.640020] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000016c42f3f state to 000000009958c70e [ 49.640055] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.640070] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 49.640084] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000446be99a state to 000000009958c70e [ 49.640144] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009958c70e [ 49.640163] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.640177] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 49.640191] [drm:dpu_crtc_destroy_state] crtc63 [ 49.640216] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 49.640231] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 49.640248] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009958c70e [ 49.640373] [drm:dpu_plane_duplicate_state] plane33 [ 49.640407] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 49.640432] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 000000004e3db5bb state to 00000000c7b1c2b4 [ 49.640480] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 49.640498] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000008f220f7 state to 00000000c7b1c2b4 [ 49.640531] DPU:KMS: mdp_snapshot: START [ 49.640536] [drm:dpu_plane_duplicate_state] plane39 [ 49.640557] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000001be180a9 state to 00000000c7b1c2b4 [ 49.640594] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 000000001be180a9 [ 49.640617] [drm:dpu_plane_duplicate_state] plane45 [ 49.640634] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000eb55b7ca state to 00000000c7b1c2b4 [ 49.640669] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 00000000eb55b7ca [ 49.640690] [drm:dpu_plane_duplicate_state] plane51 [ 49.640707] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000044538543 state to 00000000c7b1c2b4 [ 49.640741] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 0000000044538543 [ 49.640763] [drm:dpu_plane_duplicate_state] plane57 [ 49.640779] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 00000000126e7d46 state to 00000000c7b1c2b4 [ 49.640813] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 00000000126e7d46 [ 49.640839] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 000000004e3db5bb [ 49.640859] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 49.640873] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 49.640891] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 00000000c7b1c2b4 [ 49.640917] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.640930] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 49.640945] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000011b5ad1 state to 00000000c7b1c2b4 [ 49.640968] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.640984] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000011b5ad1 to [NOCRTC] [ 49.641008] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.641022] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000011b5ad1 to [CRTC:63:crtc-0] [ 49.641048] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 00000000c7b1c2b4 [ 49.641068] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 49.641083] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 49.641096] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 49.641109] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 49.641126] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 49.641141] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 49.641160] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 49.641175] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 49.641191] msm_dpu 1a01000.display-controller: [drm] layers: [ 49.641203] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 49.641220] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 49.641235] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 49.641248] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 49.641263] msm_dpu 1a01000.display-controller: [drm] name=0 [ 49.641277] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 49.641289] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 49.641305] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 49.641318] msm_dpu 1a01000.display-controller: [drm] imported=no [ 49.641333] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 49.641350] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 49.641374] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.641388] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.641401] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.641414] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.641427] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.641441] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 49.641455] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 49.641467] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.641481] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.641493] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 49.641509] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 49.641524] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 49.641537] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.641549] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.641561] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.641576] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.641596] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.641607] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.641620] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.641632] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.641644] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.641653] DPU:KMS: mdp_snapshot: DONE [ 49.641656] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.641669] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 49.641681] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.641692] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.641704] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.641718] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.641732] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 49.641745] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.641756] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.641768] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.641783] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.641801] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.641813] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.641824] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.641836] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.641848] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.641860] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.641872] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 49.641884] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.641895] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.641907] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.641921] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.641935] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 49.641948] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.641960] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.641972] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.641986] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.642005] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.642017] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.642028] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.642040] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.642052] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.642064] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.642076] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 49.642088] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.642099] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.642111] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.642124] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.642139] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 49.642151] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 49.642162] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 49.642254] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 49.642271] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 49.642290] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 49.642302] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 49.642313] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 49.642325] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 49.642337] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.642349] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 49.642361] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 49.642375] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 49.642386] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 49.642397] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 49.642412] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 49.642426] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 49.642438] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 49.642450] msm_dpu 1a01000.display-controller: [drm] active=1 [ 49.642461] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 49.642474] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 49.642486] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 49.642497] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 49.642509] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 49.642520] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 49.642532] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 49.642544] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 49.642555] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 49.642567] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 49.642596] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 49.642609] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 49.642622] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 49.642635] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 49.642647] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 49.642659] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 49.642671] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 49.642684] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 00000000c7b1c2b4 [ 49.642713] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 49.642747] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 49.642777] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 49.642803] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 0000000049d655f6 to 00000000c7b1c2b4 [ 49.642826] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000c7b1c2b4 [ 49.642851] [drm:dpu_encoder_virt_atomic_check] enc31 [ 49.642871] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 000000001169e4eb to 00000000c7b1c2b4 [ 49.642904] [drm:dpu_crtc_atomic_check] crtc63: check [ 49.642934] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 49.642967] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 49.642989] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 49.643019] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 00000000c7b1c2b4 [ 49.643043] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 49.643069] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 49.643108] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.643135] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.643157] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.643180] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0: Noisy timestamp 21 us > 20 us [3 reps]. [ 49.643222] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1645)@ 49.637013 -> 49.622881 [e 21 us, 3 rep] [ 49.643270] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.643292] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.643314] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.643337] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0: Noisy timestamp 21 us > 20 us [3 reps]. [ 49.643371] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1663)@ 49.637170 -> 49.622883 [e 21 us, 3 rep] [ 49.643417] DPU:KMS: dpu_kms_enable_commit [ 49.643424] DPU:KMS: dpu_kms_wait_flush [ 49.643430] DPU:KMS: dpu_kms_wait_for_commit_done [ 49.643437] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 49.643455] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.643477] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.670425] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 49.670495] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:49664289304 [ 49.699136] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.699187] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.699213] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 49.699231] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 49.699254] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 49.699299] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 49.699333] [drm:dpu_crtc_atomic_begin] crtc63 [ 49.699364] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.699387] [drm:_dpu_crtc_blend_setup] crtc63 [ 49.699413] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 49.699438] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 49.699462] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 49.699485] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 49.699508] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 49.699531] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 49.699554] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 49.699576] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 49.699599] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 49.699624] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 49.699657] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 49.699682] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 49.699705] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 49.699728] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 49.699763] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 49.699786] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 49.699810] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 49.699832] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 49.699853] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 49.699876] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 49.699903] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 49.699928] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 49.699951] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 49.699973] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 49.699996] [drm:dpu_plane_atomic_update] plane33 [ 49.700016] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 49.700056] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 49.700082] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 49.700105] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 49.700128] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 49.700150] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 49.700174] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 49.700196] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 49.700219] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 49.700241] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 49.700263] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 49.700289] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 49.700313] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 49.700335] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 49.700358] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 49.700380] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 49.700402] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 49.700425] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 49.700447] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 49.700470] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 49.700494] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 49.700516] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 49.700537] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 49.700561] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 49.700584] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 49.700606] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 49.700631] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 49.700652] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 49.700676] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 49.700698] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 49.700719] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 49.700739] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 49.700765] [drm:dpu_crtc_atomic_flush] crtc63 [ 49.700790] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 49.700823] DPU:KMS: dpu_kms_flush_commit [ 49.700831] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.700854] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.700960] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.701063] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.701165] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.701265] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.701364] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.701463] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.701562] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.701661] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.701760] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.701859] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.701958] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.702057] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.702156] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.702301] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.702405] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.702504] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.702604] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.702705] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.702807] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 49.702905] hw recovery is not complete for ctl:1 [ 49.702916] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 49.702937] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 49.702956] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 49.702971] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 49.702993] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 49.703014] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 49.703042] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.703063] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 49.703089] DPU:KMS: dpu_kms_wait_flush [ 49.703094] DPU:KMS: dpu_kms_wait_for_commit_done [ 49.703100] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 49.703118] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.703139] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.759124] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.759161] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 49.759185] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 49.759200] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 49.759215] DPU:KMS: dpu_kms_complete_comit [ 49.759221] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 49.759253] [drm:dpu_crtc_complete_commit] crtc63: send event: 000000000aff3ec0 [ 49.759282] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 49.759314] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000c7b1c2b4 [ 49.759338] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.759358] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 49.759373] [drm:dpu_crtc_destroy_state] crtc63 [ 49.759399] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 49.759415] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 49.759437] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 00000000c7b1c2b4 [ 49.759714] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009958c70e [ 49.759750] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 49.759773] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000016c42f3f state to 000000009958c70e [ 49.759813] [drm:dpu_plane_duplicate_state] plane33 [ 49.759833] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 49.759850] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000081dd1a9d state to 000000009958c70e [ 49.759885] [drm:dpu_plane_duplicate_state] plane39 [ 49.759902] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000004c5d1e92 state to 000000009958c70e [ 49.759934] [drm:dpu_plane_duplicate_state] plane45 [ 49.759950] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000afe6e5c7 state to 000000009958c70e [ 49.759982] [drm:dpu_plane_duplicate_state] plane51 [ 49.759997] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000098756489 state to 000000009958c70e [ 49.760029] [drm:dpu_plane_duplicate_state] plane57 [ 49.760044] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000029eeaabd state to 000000009958c70e [ 49.760079] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.760094] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 49.760109] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 0000000025464e05 state to 000000009958c70e [ 49.760156] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009958c70e [ 49.760174] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.760190] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 49.760203] [drm:dpu_crtc_destroy_state] crtc63 [ 49.760229] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 49.760243] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 49.760261] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009958c70e [ 49.760532] DPU:KMS: mdp_snapshot: START [ 49.761622] DPU:KMS: mdp_snapshot: DONE [ 49.761635] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009958c70e [ 49.761656] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 49.761673] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000029eeaabd state to 000000009958c70e [ 49.761705] [drm:dpu_plane_duplicate_state] plane33 [ 49.761721] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 49.761735] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000098756489 state to 000000009958c70e [ 49.761767] [drm:dpu_plane_duplicate_state] plane39 [ 49.761783] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000afe6e5c7 state to 000000009958c70e [ 49.761815] [drm:dpu_plane_duplicate_state] plane45 [ 49.761830] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000004c5d1e92 state to 000000009958c70e [ 49.761861] [drm:dpu_plane_duplicate_state] plane51 [ 49.761877] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000081dd1a9d state to 000000009958c70e [ 49.761908] [drm:dpu_plane_duplicate_state] plane57 [ 49.761924] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000016c42f3f state to 000000009958c70e [ 49.761957] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 49.761970] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 49.761984] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000a86eb5ab state to 000000009958c70e [ 49.762017] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009958c70e [ 49.762034] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 49.762048] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 49.762061] [drm:dpu_crtc_destroy_state] crtc63 [ 49.762086] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 49.762099] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 49.762115] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009958c70e [ 49.775571] device: 'vcs2': device_add [ 49.775669] PM: Adding info for No Bus:vcs2 [ 49.776353] device: 'vcsu2': device_add [ 49.776418] PM: Adding info for No Bus:vcsu2 [ 49.777050] device: 'vcsa2': device_add [ 49.777123] PM: Adding info for No Bus:vcsa2 [ 49.780255] device: 'vcs3': device_add [ 49.780477] PM: Adding info for No Bus:vcs3 [ 49.781579] device: 'vcsu3': device_add [ 49.781766] PM: Adding info for No Bus:vcsu3 [ 49.782683] device: 'vcsa3': device_add [ 49.782909] PM: Adding info for No Bus:vcsa3 [ 49.786380] device: 'vcs4': device_add [ 49.786619] PM: Adding info for No Bus:vcs4 [ 49.787442] device: 'vcsu4': device_add [ 49.787631] PM: Adding info for No Bus:vcsu4 [ 49.788533] device: 'vcsa4': device_add [ 49.788983] PM: Adding info for No Bus:vcsa4 [ 49.790205] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 49.790303] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:49784079876 [ 49.793733] device: 'vcs5': device_add [ 49.793825] PM: Adding info for No Bus:vcs5 [ 49.794156] device: 'vcsu5': device_add [ 49.794304] PM: Adding info for No Bus:vcsu5 [ 49.794857] device: 'vcsa5': device_add [ 49.794929] PM: Adding info for No Bus:vcsa5 [ 49.797491] device: 'vcs6': device_add [ 49.797704] PM: Adding info for No Bus:vcs6 [ 49.798124] device: 'vcsu6': device_add [ 49.798612] PM: Adding info for No Bus:vcsu6 [ 49.799639] device: 'vcsa6': device_add [ 49.799823] PM: Adding info for No Bus:vcsa6 [ 50.314294] cpu cpu4: _set_opp: switching OPP: Freq 400000000 -> 1190400000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 50.466242] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 0000000030193ece [ 50.466269] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 50.466279] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000006f973e3b state to 0000000030193ece [ 50.466296] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 0000000030193ece [ 50.466309] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 50.466316] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 50.466321] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000f8c6cdc2 state to 0000000030193ece [ 50.466332] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 0000000030193ece [ 50.466339] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 50.466346] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 50.466351] [drm:dpu_crtc_destroy_state] crtc63 [ 50.466362] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 50.466369] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 0000000030193ece [ 50.901712] cpu cpu0: _set_opp: switching OPP: Freq 200000000 -> 1017600000 Hz, Level 4294967295 -> 4294967295, Bw 0 -> 0 [ 52.001971] [drm:drm_stub_open] [ 52.002016] msm_dpu 1a01000.display-controller: [drm:drm_open_helper] comm="elogind", pid=3821, minor=0 [ 52.002055] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="elogind" pid=3821, dev=0xe200, auth=1, DRM_IOCTL_SET_MASTER [ 52.002858] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES [ 52.003483] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_VERSION [ 52.003503] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_VERSION [ 52.003541] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 52.003555] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 52.003567] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 52.003579] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_SET_CLIENT_CAP [ 52.003591] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 52.003603] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_SET_CLIENT_CAP [ 52.003620] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 52.003632] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_GET_CAP [ 52.003649] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES [ 52.003663] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES [ 52.003683] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCRTC [ 52.003701] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.003717] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.003735] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003749] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003763] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003775] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003789] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003801] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003814] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003826] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003840] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES [ 52.003855] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANERESOURCES [ 52.003874] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 52.003889] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 52.003905] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.003921] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.003940] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003955] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003970] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003982] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.003995] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004007] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004021] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004033] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004046] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004057] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004072] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004084] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004097] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004109] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004122] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004134] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004147] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004159] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004173] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004185] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004198] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004210] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004223] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004235] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004247] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004259] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004272] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004284] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004297] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004309] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004322] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004335] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004350] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004364] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004380] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004392] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004406] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.004421] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.004463] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.004478] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.004495] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 52.004507] [drm:drm_mode_object_put.part.0] OBJ ID: 34 (2) [ 52.004516] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 52.004527] [drm:drm_mode_object_put.part.0] OBJ ID: 34 (2) [ 52.004548] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 52.004563] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 52.004578] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.004594] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.004611] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004624] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004639] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004651] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004664] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004677] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004690] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004702] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004716] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004728] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004740] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004753] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004766] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004778] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004791] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004803] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004816] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004828] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004841] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004853] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004867] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004879] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004892] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004904] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004917] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004929] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004942] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004954] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004967] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004979] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.004993] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005007] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005021] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005035] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005051] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005063] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005077] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.005092] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.005110] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 52.005123] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 52.005138] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.005154] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.005170] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005183] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005198] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005210] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005223] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005235] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005249] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005261] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005274] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005286] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005299] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005312] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005325] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005337] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005350] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005362] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005375] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005387] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005400] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005413] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005426] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005438] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005451] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005463] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005476] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005488] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005500] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005513] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005526] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005538] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005551] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005565] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005579] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005593] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005609] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005622] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005636] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.005650] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.005667] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 52.005681] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 52.005696] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.005710] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.005727] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005740] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005755] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005767] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005780] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005792] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005805] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005817] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005830] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005843] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005856] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005868] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005881] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005893] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005906] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005918] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005931] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005944] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005957] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005969] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005982] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.005994] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006007] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006019] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006032] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006044] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006057] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006069] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006082] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006094] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006107] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006121] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006136] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006150] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006208] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006224] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006238] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.006254] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.006272] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 52.006286] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPLANE [ 52.006301] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.006315] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.006332] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006344] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006358] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006370] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006383] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006395] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006408] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006420] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006433] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006445] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006457] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006469] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006482] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006494] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006507] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006519] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006532] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006544] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006557] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006569] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006581] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006593] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006606] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006619] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006632] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006644] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006657] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006669] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006682] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006694] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006707] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006721] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006736] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006749] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006764] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006777] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY [ 52.006790] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.006804] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.006833] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.006848] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES [ 52.006865] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 52.006876] [drm:drm_mode_object_put.part.0] OBJ ID: 58 (2) [ 52.006884] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPBLOB [ 52.006895] [drm:drm_mode_object_put.part.0] OBJ ID: 58 (2) [ 52.008666] [drm:drm_stub_open] [ 52.008683] msm_dpu 1a01000.display-controller: [drm:drm_open_helper] comm="phoc", pid=4476, minor=128 [ 52.008708] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 52.008725] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 52.013861] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 52.013891] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 52.157402] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 52.157438] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 52.162375] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 52.162403] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 52.162596] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 52.162613] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, DRM_IOCTL_VERSION [ 52.162647] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, MSM_GEM_NEW [ 52.162661] msm_dpu 1a01000.display-controller: [drm:msm_gem_new_impl.isra.0] invalid cache flag: 80000 [ 52.162674] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4476, ret=-22 [ 52.162721] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, MSM_GET_PARAM [ 52.162734] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4476, ret=-6 [ 52.162788] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, MSM_GET_PARAM [ 52.162800] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4476, ret=-6 [ 52.162821] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, MSM_GET_PARAM [ 52.162833] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4476, ret=-6 [ 52.162852] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc" pid=4476, dev=0xe280, auth=0, MSM_GET_PARAM [ 52.162863] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="phoc", pid=4476, ret=-6 [ 52.169028] msm_dpu 1a01000.display-controller: [drm:drm_release] open_count = 2 [ 52.169054] msm_dpu 1a01000.display-controller: [drm:drm_file_free] comm="phoc", pid=4476, dev=0xe280, open_count=2 [ 52.171144] msm_dpu 1a01000.display-controller: [drm:drm_ioctl] comm="elogind" pid=3821, dev=0xe200, auth=1, DRM_IOCTL_DROP_MASTER [ 52.171198] msm_dpu 1a01000.display-controller: [drm:drm_release] open_count = 1 [ 52.171214] msm_dpu 1a01000.display-controller: [drm:drm_file_free] comm="elogind", pid=3821, dev=0xe200, open_count=1 [ 52.171235] msm_dpu 1a01000.display-controller: [drm:_drm_lease_revoke] revoke leases for 0000000011992f75 0 [ 52.171256] msm_dpu 1a01000.display-controller: [drm:drm_lease_destroy] drm_lease_destroy 0 [ 52.171270] msm_dpu 1a01000.display-controller: [drm:drm_lease_destroy] drm_lease_destroy done 0 [ 52.171290] msm_dpu 1a01000.display-controller: [drm:drm_lastclose] [ 52.171302] msm_dpu 1a01000.display-controller: [drm:drm_lastclose] driver lastclose completed [ 52.171321] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 0000000013d4471b [ 52.171340] [drm:dpu_plane_duplicate_state] plane33 [ 52.171353] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 52.171364] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 000000005f998769 state to 0000000013d4471b [ 52.171386] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 52.171396] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 00000000d05cc508 state to 0000000013d4471b [ 52.171415] [drm:dpu_plane_duplicate_state] plane39 [ 52.171425] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000000e620d3d state to 0000000013d4471b [ 52.171444] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 000000000e620d3d [ 52.171458] [drm:dpu_plane_duplicate_state] plane45 [ 52.171468] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000002b5375e3 state to 0000000013d4471b [ 52.171486] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 000000002b5375e3 [ 52.171500] [drm:dpu_plane_duplicate_state] plane51 [ 52.171510] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000080770e55 state to 0000000013d4471b [ 52.171528] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 0000000080770e55 [ 52.171541] [drm:dpu_plane_duplicate_state] plane57 [ 52.171551] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000095ea3066 state to 0000000013d4471b [ 52.171570] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 0000000095ea3066 [ 52.171588] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 000000005f998769 [ 52.171602] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 52.171610] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 52.171624] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 0000000013d4471b [ 52.171641] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.171650] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 52.171660] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 0000000011992f75 state to 0000000013d4471b [ 52.171673] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.171683] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 0000000011992f75 to [NOCRTC] [ 52.171697] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.171706] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 0000000011992f75 to [CRTC:63:crtc-0] [ 52.171721] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 0000000013d4471b [ 52.171733] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 52.171742] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 52.171750] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 52.171758] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 52.171767] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 52.171775] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 52.171787] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 52.171796] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 52.171805] msm_dpu 1a01000.display-controller: [drm] layers: [ 52.171813] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 52.171824] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 52.171832] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 52.171842] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 52.171852] msm_dpu 1a01000.display-controller: [drm] name=0 [ 52.171860] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 52.171869] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 52.171877] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 52.171886] msm_dpu 1a01000.display-controller: [drm] imported=no [ 52.171894] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 52.171904] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 52.171917] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.171925] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.171933] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.171941] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.171949] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.171958] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 52.171966] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 52.171974] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.171982] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.171990] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 52.171999] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 52.172009] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 52.172017] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.172025] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.172033] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.172042] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.172054] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.172062] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.172069] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.172077] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.172085] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.172092] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.172100] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 52.172109] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.172116] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.172124] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.172133] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.172142] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 52.172150] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.172157] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.172165] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.172174] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.172186] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.172194] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.172201] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.172209] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.172217] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.172224] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.172232] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 52.172239] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.172247] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.172255] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.172264] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.172273] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 52.172282] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.172289] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.172296] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.172306] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.172318] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.172326] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.172334] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.172341] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.172349] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.172357] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.172365] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 52.172373] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.172380] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.172388] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.172397] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.172406] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 52.172414] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.172422] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.172429] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.172438] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.172450] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.172458] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.172465] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.172473] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.172481] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.172488] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.172496] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 52.172504] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.172512] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.172519] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.172528] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.172538] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 52.172546] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 52.172554] msm_dpu 1a01000.display-controller: [drm] active=1 [ 52.172562] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 52.172570] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 52.172578] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 52.172586] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 52.172593] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 52.172601] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.172609] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 52.172616] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 52.172624] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 52.172632] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 52.172650] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 52.172659] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 52.172668] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 52.172676] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 52.172683] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 52.172691] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 52.172699] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 52.172708] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 0000000013d4471b [ 52.172734] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 52.172755] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 52.172775] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000013d4471b [ 52.172794] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 000000005acaee25 to 0000000013d4471b [ 52.172809] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000013d4471b [ 52.172828] [drm:dpu_encoder_virt_atomic_check] enc31 [ 52.172844] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 0000000061a94ca7 to 0000000013d4471b [ 52.172873] [drm:dpu_crtc_atomic_check] crtc63: check [ 52.172890] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 52.172908] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 52.172920] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 52.172940] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 0000000013d4471b [ 52.172959] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 52.172977] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 52.173001] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.173020] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1220)@ 52.166852 -> 52.156371 [e 18 us, 0 rep] [ 52.173054] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.173067] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1226)@ 52.166901 -> 52.156368 [e 12 us, 0 rep] [ 52.173096] DPU:KMS: dpu_kms_enable_commit [ 52.173103] DPU:KMS: dpu_kms_wait_flush [ 52.173107] DPU:KMS: dpu_kms_wait_for_commit_done [ 52.173111] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 52.173122] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.173135] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.226600] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.226639] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.226651] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 52.226662] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 52.226680] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 52.226703] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 52.226723] [drm:dpu_crtc_atomic_begin] crtc63 [ 52.226738] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.226751] [drm:_dpu_crtc_blend_setup] crtc63 [ 52.226767] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 52.226781] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 52.226794] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 52.226807] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 52.226820] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 52.226833] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 52.226845] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 52.226858] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 52.226871] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 52.226887] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 52.226906] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 52.226920] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 52.226933] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 52.226946] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 52.226966] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 52.226977] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 52.226992] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 52.227005] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 52.227016] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 52.227030] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 52.227046] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 52.227058] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 52.227071] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 52.227084] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 52.227099] [drm:dpu_plane_atomic_update] plane33 [ 52.227112] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 52.227134] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 52.227148] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 52.227161] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 52.227173] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 52.227186] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 52.227200] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 52.227213] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 52.227226] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 52.227239] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 52.227252] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 52.227268] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 52.227282] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 52.227295] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 52.227309] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 52.227322] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 52.227335] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 52.227349] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 52.227362] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 52.227374] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 52.227389] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 52.227401] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 52.227413] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 52.227428] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 52.227441] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 52.227454] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 52.227469] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 52.227480] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 52.227496] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.227508] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 52.227520] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 52.227532] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 52.227550] [drm:dpu_crtc_atomic_flush] crtc63 [ 52.227564] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 52.227585] DPU:KMS: dpu_kms_flush_commit [ 52.227590] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.227604] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.227684] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.227764] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.227843] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.227921] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.227999] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228077] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228155] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228233] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228310] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228388] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228466] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228543] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228621] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228698] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228776] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228853] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.228931] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.229008] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.229087] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.229164] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.229243] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.229320] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.229397] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.229474] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.229552] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.229629] hw recovery is not complete for ctl:1 [ 52.229638] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 52.229659] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 52.229671] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 52.229680] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 52.229692] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 52.229704] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 52.229721] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.229733] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 52.229749] DPU:KMS: dpu_kms_wait_flush [ 52.229751] DPU:KMS: dpu_kms_wait_for_commit_done [ 52.229756] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 52.229766] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.229777] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.229979] DPU:KMS: mdp_snapshot: START [ 52.230927] DPU:KMS: mdp_snapshot: DONE [ 52.282592] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.282616] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.282629] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 52.282638] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 52.282647] DPU:KMS: dpu_kms_complete_comit [ 52.282651] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 52.282668] [drm:dpu_crtc_complete_commit] crtc63: send event: 00000000716f723b [ 52.282690] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 52.282714] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 0000000013d4471b [ 52.282730] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.282743] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 52.282753] [drm:dpu_crtc_destroy_state] crtc63 [ 52.282767] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 52.282778] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 52.282798] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 0000000013d4471b [ 52.282823] msm_dpu 1a01000.display-controller: [drm:drm_client_dev_restore] fbdev: ret=0 [ 52.282953] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009958c70e [ 52.282969] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 52.282978] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000000b483c46 state to 000000009958c70e [ 52.282995] [drm:dpu_plane_duplicate_state] plane33 [ 52.283003] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 52.283009] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 000000003f74cf12 state to 000000009958c70e [ 52.283022] [drm:dpu_plane_duplicate_state] plane39 [ 52.283029] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000b634428e state to 000000009958c70e [ 52.283041] [drm:dpu_plane_duplicate_state] plane45 [ 52.283048] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000008f19c61d state to 000000009958c70e [ 52.283059] [drm:dpu_plane_duplicate_state] plane51 [ 52.283065] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 000000004fc13beb state to 000000009958c70e [ 52.283077] [drm:dpu_plane_duplicate_state] plane57 [ 52.283083] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 000000000e3c0e61 state to 000000009958c70e [ 52.283097] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.283102] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 52.283108] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000c88fa867 state to 000000009958c70e [ 52.283132] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009958c70e [ 52.283139] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.283145] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 52.283151] [drm:dpu_crtc_destroy_state] crtc63 [ 52.283160] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 52.283166] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 52.283173] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009958c70e [ 52.283257] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 0000000013d4471b [ 52.283275] [drm:dpu_plane_duplicate_state] plane33 [ 52.283284] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 52.283294] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000fceee8c1 state to 0000000013d4471b [ 52.283312] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 52.283321] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 00000000256ed2e1 state to 0000000013d4471b [ 52.283338] [drm:dpu_plane_duplicate_state] plane39 [ 52.283347] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000009966f190 state to 0000000013d4471b [ 52.283365] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 000000009966f190 [ 52.283377] [drm:dpu_plane_duplicate_state] plane45 [ 52.283386] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000008a415397 state to 0000000013d4471b [ 52.283403] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 000000008a415397 [ 52.283415] [drm:dpu_plane_duplicate_state] plane51 [ 52.283423] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000048b361fd state to 0000000013d4471b [ 52.283440] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 0000000048b361fd [ 52.283465] [drm:dpu_plane_duplicate_state] plane57 [ 52.283474] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 00000000fe11af25 state to 0000000013d4471b [ 52.283492] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 00000000fe11af25 [ 52.283508] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 00000000fceee8c1 [ 52.283521] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 52.283528] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 52.283538] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 0000000013d4471b [ 52.283553] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.283560] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 52.283568] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 0000000038550da2 state to 0000000013d4471b [ 52.283582] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.283591] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 0000000038550da2 to [NOCRTC] [ 52.283603] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.283611] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 0000000038550da2 to [CRTC:63:crtc-0] [ 52.283625] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 0000000013d4471b [ 52.283636] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 52.283644] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 52.283650] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 52.283658] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 52.283665] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 52.283672] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 52.283682] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 52.283689] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 52.283697] msm_dpu 1a01000.display-controller: [drm] layers: [ 52.283703] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 52.283712] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 52.283719] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 52.283727] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 52.283735] msm_dpu 1a01000.display-controller: [drm] name=0 [ 52.283742] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 52.283749] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 52.283756] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 52.283763] msm_dpu 1a01000.display-controller: [drm] imported=no [ 52.283771] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 52.283779] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 52.283791] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.283797] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.283804] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.283811] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.283819] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.283826] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 52.283833] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 52.283839] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.283846] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.283853] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 52.283861] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 52.283870] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 52.283877] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.283884] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.283890] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.283898] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.283909] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.283916] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.283922] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.283929] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.283935] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.283942] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.283949] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 52.283956] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.283963] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.283969] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.283977] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.283985] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 52.283993] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.283999] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.284005] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.284014] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.284025] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.284031] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.284038] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.284044] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.284050] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.284057] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.284064] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 52.284071] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.284077] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.284083] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.284092] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.284100] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 52.284107] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.284113] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.284120] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.284128] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.284139] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.284146] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.284152] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.284159] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.284165] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.284172] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.284179] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 52.284185] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.284192] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.284198] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.284206] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.284214] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 52.284222] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.284228] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.284234] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.284243] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.284253] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.284260] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.284266] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.284273] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.284279] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.284286] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.284293] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 52.284299] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.284306] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.284312] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.284320] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.284328] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 52.284335] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 52.284342] msm_dpu 1a01000.display-controller: [drm] active=1 [ 52.284349] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 52.284356] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 52.284362] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 52.284369] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 52.284375] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 52.284382] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.284389] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 52.284395] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 52.284402] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 52.284410] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 52.284426] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 52.284433] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 52.284441] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 52.284448] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 52.284455] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 52.284462] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 52.284469] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 52.284476] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 0000000013d4471b [ 52.284496] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 52.284512] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 52.284529] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000013d4471b [ 52.284545] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 000000009615f78b to 0000000013d4471b [ 52.284558] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000013d4471b [ 52.284573] [drm:dpu_encoder_virt_atomic_check] enc31 [ 52.284584] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 00000000bfded4d1 to 0000000013d4471b [ 52.284609] [drm:dpu_crtc_atomic_check] crtc63: check [ 52.284625] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 52.284641] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 52.284651] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 52.284670] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 0000000013d4471b [ 52.284686] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 52.284702] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 52.284723] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.284740] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,644)@ 52.278572 -> 52.273040 [e 15 us, 0 rep] [ 52.284767] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.284779] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,649)@ 52.278613 -> 52.273037 [e 11 us, 0 rep] [ 52.284805] DPU:KMS: dpu_kms_enable_commit [ 52.284810] DPU:KMS: dpu_kms_wait_flush [ 52.284813] DPU:KMS: dpu_kms_wait_for_commit_done [ 52.284815] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 52.284825] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.284837] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.314312] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 52.314478] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:52308161855 [ 52.338338] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.338355] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.338367] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 52.338375] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 52.338388] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 52.338407] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 52.338424] [drm:dpu_crtc_atomic_begin] crtc63 [ 52.338437] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.338448] [drm:_dpu_crtc_blend_setup] crtc63 [ 52.338461] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 52.338473] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 52.338485] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 52.338497] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 52.338509] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 52.338520] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 52.338532] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 52.338543] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 52.338555] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 52.338569] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 52.338587] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 52.338600] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 52.338612] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 52.338624] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 52.338642] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 52.338652] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 52.338665] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 52.338677] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 52.338688] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 52.338700] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 52.338715] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 52.338727] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 52.338738] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 52.338750] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 52.338763] [drm:dpu_plane_atomic_update] plane33 [ 52.338774] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 52.338795] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 52.338807] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 52.338820] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 52.338831] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 52.338843] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 52.338855] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 52.338867] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 52.338879] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 52.338890] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 52.338903] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 52.338918] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 52.338931] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 52.338943] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 52.338955] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 52.338967] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 52.338979] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 52.338991] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 52.339003] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 52.339015] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 52.339029] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 52.339041] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 52.339051] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 52.339064] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 52.339076] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 52.339088] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 52.339101] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 52.339112] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 52.339127] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.339138] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 52.339148] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 52.339158] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 52.339173] [drm:dpu_crtc_atomic_flush] crtc63 [ 52.339185] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 52.339205] DPU:KMS: dpu_kms_flush_commit [ 52.339211] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339222] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339302] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339381] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339458] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339535] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339612] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339690] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339767] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339844] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339920] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.339997] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340073] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340150] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340226] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340302] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340380] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340456] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340533] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340609] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340687] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340764] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340842] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340919] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.340997] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.341073] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.341149] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.341225] hw recovery is not complete for ctl:1 [ 52.341231] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 52.341249] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 52.341260] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 52.341269] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 52.341280] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 52.341291] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 52.341307] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.341317] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 52.341331] DPU:KMS: dpu_kms_wait_flush [ 52.341333] DPU:KMS: dpu_kms_wait_for_commit_done [ 52.341336] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 52.341344] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.341355] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.341563] DPU:KMS: mdp_snapshot: START [ 52.342500] DPU:KMS: mdp_snapshot: DONE [ 52.394545] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.394564] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.394575] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 52.394582] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 52.394591] DPU:KMS: dpu_kms_complete_comit [ 52.394594] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 52.394609] [drm:dpu_crtc_complete_commit] crtc63: send event: 00000000716f723b [ 52.394626] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 52.394650] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 0000000013d4471b [ 52.394662] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.394672] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 52.394680] [drm:dpu_crtc_destroy_state] crtc63 [ 52.394693] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 52.394704] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 52.394723] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 0000000013d4471b [ 52.394751] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 0000000013d4471b [ 52.394764] [drm:dpu_plane_duplicate_state] plane33 [ 52.394772] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 52.394781] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000043418985 state to 0000000013d4471b [ 52.394800] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 52.394808] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 00000000d56faae4 state to 0000000013d4471b [ 52.394826] [drm:dpu_plane_duplicate_state] plane39 [ 52.394834] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000003625a2ec state to 0000000013d4471b [ 52.394852] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 000000003625a2ec [ 52.394866] [drm:dpu_plane_duplicate_state] plane45 [ 52.394875] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 0000000098d44a70 state to 0000000013d4471b [ 52.394892] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 0000000098d44a70 [ 52.394904] [drm:dpu_plane_duplicate_state] plane51 [ 52.394912] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 000000007752edc6 state to 0000000013d4471b [ 52.394929] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 000000007752edc6 [ 52.394941] [drm:dpu_plane_duplicate_state] plane57 [ 52.394949] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 00000000c343b05e state to 0000000013d4471b [ 52.394966] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 00000000c343b05e [ 52.394983] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 0000000043418985 [ 52.394995] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 52.395003] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 52.395014] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 0000000013d4471b [ 52.395024] [drm:dpu_crtc_destroy_state] crtc63 [ 52.395035] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 52.395043] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 52.395192] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009958c70e [ 52.395204] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 52.395212] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000000e3c0e61 state to 000000009958c70e [ 52.395226] [drm:dpu_plane_duplicate_state] plane33 [ 52.395232] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 52.395238] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 000000004fc13beb state to 000000009958c70e [ 52.395250] [drm:dpu_plane_duplicate_state] plane39 [ 52.395256] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000008f19c61d state to 000000009958c70e [ 52.395268] [drm:dpu_plane_duplicate_state] plane45 [ 52.395273] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000b634428e state to 000000009958c70e [ 52.395284] [drm:dpu_plane_duplicate_state] plane51 [ 52.395290] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 000000003f74cf12 state to 000000009958c70e [ 52.395301] [drm:dpu_plane_duplicate_state] plane57 [ 52.395307] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 000000000b483c46 state to 000000009958c70e [ 52.395319] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.395324] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 52.395330] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000a5f3c4e9 state to 000000009958c70e [ 52.395353] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009958c70e [ 52.395359] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.395364] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 52.395369] [drm:dpu_crtc_destroy_state] crtc63 [ 52.395378] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 52.395383] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 52.395388] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009958c70e [ 52.395483] [drm:dpu_plane_duplicate_state] plane33 [ 52.395497] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 52.395506] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000c343b05e state to 0000000013d4471b [ 52.395525] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 52.395534] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000007752edc6 state to 0000000013d4471b [ 52.395552] [drm:dpu_plane_duplicate_state] plane39 [ 52.395560] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 0000000098d44a70 state to 0000000013d4471b [ 52.395578] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 0000000098d44a70 [ 52.395590] [drm:dpu_plane_duplicate_state] plane45 [ 52.395599] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000003625a2ec state to 0000000013d4471b [ 52.395616] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 000000003625a2ec [ 52.395628] [drm:dpu_plane_duplicate_state] plane51 [ 52.395636] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 0000000043418985 state to 0000000013d4471b [ 52.395654] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 0000000043418985 [ 52.395666] [drm:dpu_plane_duplicate_state] plane57 [ 52.395674] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 00000000d56faae4 state to 0000000013d4471b [ 52.395691] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 00000000d56faae4 [ 52.395705] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 00000000c343b05e [ 52.395717] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 52.395724] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 52.395734] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 0000000013d4471b [ 52.395749] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.395756] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 52.395764] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 0000000061a94ca7 state to 0000000013d4471b [ 52.395776] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.395785] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 0000000061a94ca7 to [NOCRTC] [ 52.395798] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.395806] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 0000000061a94ca7 to [CRTC:63:crtc-0] [ 52.395821] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 0000000013d4471b [ 52.395833] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 52.395840] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 52.395847] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 52.395854] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 52.395862] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 52.395869] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 52.395879] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 52.395886] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 52.395895] msm_dpu 1a01000.display-controller: [drm] layers: [ 52.395902] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 52.395910] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 52.395918] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 52.395926] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 52.395934] msm_dpu 1a01000.display-controller: [drm] name=0 [ 52.395942] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 52.395949] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 52.395957] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 52.395965] msm_dpu 1a01000.display-controller: [drm] imported=no [ 52.395972] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 52.395982] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 52.395993] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.396000] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.396007] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.396014] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.396022] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.396029] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 52.396036] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 52.396043] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.396050] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.396056] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 52.396065] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 52.396075] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 52.396082] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.396089] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.396095] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.396104] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.396114] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.396121] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.396127] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.396134] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.396141] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.396148] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.396155] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 52.396161] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.396168] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.396174] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.396182] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.396191] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 52.396198] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.396205] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.396211] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.396220] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.396230] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.396237] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.396243] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.396250] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.396257] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.396264] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.396270] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 52.396277] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.396283] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.396290] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.396298] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.396306] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 52.396314] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.396320] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.396327] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.396335] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.396346] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.396352] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.396359] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.396366] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.396373] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.396379] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.396386] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 52.396393] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.396399] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.396406] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.396414] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.396422] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 52.396430] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.396436] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.396443] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.396451] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.396462] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.396468] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.396475] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.396482] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.396489] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.396495] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.396502] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 52.396508] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.396515] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.396521] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.396529] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.396538] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 52.396545] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 52.396552] msm_dpu 1a01000.display-controller: [drm] active=1 [ 52.396558] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 52.396565] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 52.396572] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 52.396578] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 52.396585] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 52.396592] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.396599] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 52.396606] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 52.396612] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 52.396619] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 52.396635] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 52.396643] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 52.396650] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 52.396658] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 52.396665] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 52.396671] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 52.396679] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 52.396687] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 0000000013d4471b [ 52.396706] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 52.396723] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 52.396741] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000013d4471b [ 52.396758] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 00000000725acd1a to 0000000013d4471b [ 52.396771] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000013d4471b [ 52.396789] [drm:dpu_encoder_virt_atomic_check] enc31 [ 52.396800] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 00000000fda56812 to 0000000013d4471b [ 52.396824] [drm:dpu_crtc_atomic_check] crtc63: check [ 52.396839] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 52.396854] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 52.396865] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 52.396883] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 0000000013d4471b [ 52.396899] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 52.396915] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 52.396937] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.396952] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,125)@ 52.390785 -> 52.389711 [e 14 us, 0 rep] [ 52.396979] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.396992] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,129)@ 52.390825 -> 52.389717 [e 11 us, 0 rep] [ 52.397017] DPU:KMS: dpu_kms_enable_commit [ 52.397020] DPU:KMS: dpu_kms_wait_flush [ 52.397024] DPU:KMS: dpu_kms_wait_for_commit_done [ 52.397026] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 52.397036] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.397047] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.426314] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 52.426531] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:52420161907 [ 52.450535] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.450552] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.450564] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 52.450571] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 52.450587] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 52.450606] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 52.450624] [drm:dpu_crtc_atomic_begin] crtc63 [ 52.450637] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.450648] [drm:_dpu_crtc_blend_setup] crtc63 [ 52.450660] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 52.450674] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 52.450686] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 52.450698] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 52.450710] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 52.450721] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 52.450733] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 52.450745] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 52.450757] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 52.450771] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 52.450789] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 52.450802] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 52.450814] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 52.450826] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 52.450844] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 52.450854] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 52.450867] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 52.450879] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 52.450890] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 52.450902] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 52.450916] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 52.450928] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 52.450939] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 52.450951] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 52.450964] [drm:dpu_plane_atomic_update] plane33 [ 52.450975] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 52.450995] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 52.451008] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 52.451020] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 52.451031] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 52.451043] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 52.451056] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 52.451068] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 52.451080] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 52.451092] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 52.451104] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 52.451119] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 52.451132] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 52.451144] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 52.451156] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 52.451168] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 52.451180] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 52.451192] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 52.451205] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 52.451216] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 52.451230] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 52.451242] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 52.451253] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 52.451265] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 52.451277] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 52.451289] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 52.451302] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 52.451312] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 52.451327] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.451339] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 52.451349] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 52.451359] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 52.451374] [drm:dpu_crtc_atomic_flush] crtc63 [ 52.451386] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 52.451404] DPU:KMS: dpu_kms_flush_commit [ 52.451408] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.451420] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.451503] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.451581] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.451659] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.451736] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.451813] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.451890] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.451967] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452044] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452120] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452197] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452273] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452351] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452428] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452505] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452582] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452659] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452735] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452812] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452888] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.452966] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.453042] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.453119] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.453195] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.453272] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.453348] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.453426] hw recovery is not complete for ctl:1 [ 52.453432] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 52.453450] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 52.453461] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 52.453469] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 52.453480] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 52.453491] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 52.453506] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.453516] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 52.453531] DPU:KMS: dpu_kms_wait_flush [ 52.453533] DPU:KMS: dpu_kms_wait_for_commit_done [ 52.453536] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 52.453544] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.453555] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.453758] DPU:KMS: mdp_snapshot: START [ 52.454676] DPU:KMS: mdp_snapshot: DONE [ 52.506549] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.506568] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.506579] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 52.506587] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 52.506595] DPU:KMS: dpu_kms_complete_comit [ 52.506598] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 52.506612] [drm:dpu_crtc_complete_commit] crtc63: send event: 00000000716f723b [ 52.506629] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 52.506651] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 0000000013d4471b [ 52.506664] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.506674] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 52.506681] [drm:dpu_crtc_destroy_state] crtc63 [ 52.506693] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 52.506704] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 52.506721] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 0000000013d4471b [ 52.506786] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 0000000013d4471b [ 52.506799] [drm:dpu_plane_duplicate_state] plane33 [ 52.506807] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 52.506816] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000fe11af25 state to 0000000013d4471b [ 52.506833] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 52.506842] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 0000000005ed73ae state to 0000000013d4471b [ 52.506859] [drm:dpu_plane_duplicate_state] plane39 [ 52.506867] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000e63a166c state to 0000000013d4471b [ 52.506885] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 00000000e63a166c [ 52.506897] [drm:dpu_plane_duplicate_state] plane45 [ 52.506906] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000c5d430e3 state to 0000000013d4471b [ 52.506923] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 00000000c5d430e3 [ 52.506935] [drm:dpu_plane_duplicate_state] plane51 [ 52.506944] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 000000002fb62a34 state to 0000000013d4471b [ 52.506961] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 000000002fb62a34 [ 52.506972] [drm:dpu_plane_duplicate_state] plane57 [ 52.506981] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 000000007a4f521f state to 0000000013d4471b [ 52.506998] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 000000007a4f521f [ 52.507015] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 00000000fe11af25 [ 52.507027] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 52.507034] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 52.507045] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 0000000013d4471b [ 52.507055] [drm:dpu_crtc_destroy_state] crtc63 [ 52.507066] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 52.507074] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 52.507221] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009958c70e [ 52.507233] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 52.507241] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000000b483c46 state to 000000009958c70e [ 52.507255] [drm:dpu_plane_duplicate_state] plane33 [ 52.507261] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 52.507267] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 000000003f74cf12 state to 000000009958c70e [ 52.507279] [drm:dpu_plane_duplicate_state] plane39 [ 52.507285] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000b634428e state to 000000009958c70e [ 52.507296] [drm:dpu_plane_duplicate_state] plane45 [ 52.507302] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 000000008f19c61d state to 000000009958c70e [ 52.507313] [drm:dpu_plane_duplicate_state] plane51 [ 52.507319] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 000000004fc13beb state to 000000009958c70e [ 52.507330] [drm:dpu_plane_duplicate_state] plane57 [ 52.507335] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 000000000e3c0e61 state to 000000009958c70e [ 52.507348] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.507353] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 52.507358] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 0000000025464e05 state to 000000009958c70e [ 52.507375] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009958c70e [ 52.507382] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.507387] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 52.507392] [drm:dpu_crtc_destroy_state] crtc63 [ 52.507400] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 52.507405] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 52.507410] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009958c70e [ 52.507512] [drm:dpu_plane_duplicate_state] plane33 [ 52.507526] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 52.507537] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 000000007a4f521f state to 0000000013d4471b [ 52.507555] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 52.507564] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000002fb62a34 state to 0000000013d4471b [ 52.507581] [drm:dpu_plane_duplicate_state] plane39 [ 52.507590] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000c5d430e3 state to 0000000013d4471b [ 52.507607] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 00000000c5d430e3 [ 52.507619] [drm:dpu_plane_duplicate_state] plane45 [ 52.507628] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000e63a166c state to 0000000013d4471b [ 52.507646] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-2] state 00000000e63a166c [ 52.507658] [drm:dpu_plane_duplicate_state] plane51 [ 52.507666] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 00000000fe11af25 state to 0000000013d4471b [ 52.507684] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:51:plane-3] state 00000000fe11af25 [ 52.507696] [drm:dpu_plane_duplicate_state] plane57 [ 52.507704] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 0000000005ed73ae state to 0000000013d4471b [ 52.507722] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:57:plane-4] state 0000000005ed73ae [ 52.507735] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_fb_for_plane] Set [FB:64] for [PLANE:33:plane-0] state 000000007a4f521f [ 52.507748] [drm:drm_mode_object_get] OBJ ID: 64 (4) [ 52.507755] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (5) [ 52.507764] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 0000000013d4471b [ 52.507778] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.507786] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 52.507794] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000bfded4d1 state to 0000000013d4471b [ 52.507806] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.507816] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000bfded4d1 to [NOCRTC] [ 52.507829] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.507837] msm_dpu 1a01000.display-controller: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000bfded4d1 to [CRTC:63:crtc-0] [ 52.507852] msm_dpu 1a01000.display-controller: [drm:drm_atomic_print_new_state] checking 0000000013d4471b [ 52.507863] msm_dpu 1a01000.display-controller: [drm] plane[33]: plane-0 [ 52.507871] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 52.507877] msm_dpu 1a01000.display-controller: [drm] fb=64 [ 52.507885] msm_dpu 1a01000.display-controller: [drm] allocated by = [fbcon] [ 52.507893] msm_dpu 1a01000.display-controller: [drm] refcount=4 [ 52.507900] msm_dpu 1a01000.display-controller: [drm] format=XR24 little-endian (0x34325258) [ 52.507910] msm_dpu 1a01000.display-controller: [drm] modifier=0x0 [ 52.507917] msm_dpu 1a01000.display-controller: [drm] size=1080x1920 [ 52.507925] msm_dpu 1a01000.display-controller: [drm] layers: [ 52.507932] msm_dpu 1a01000.display-controller: [drm] size[0]=1080x1920 [ 52.507941] msm_dpu 1a01000.display-controller: [drm] pitch[0]=4352 [ 52.507949] msm_dpu 1a01000.display-controller: [drm] offset[0]=0 [ 52.507957] msm_dpu 1a01000.display-controller: [drm] obj[0]: [ 52.507966] msm_dpu 1a01000.display-controller: [drm] name=0 [ 52.507974] msm_dpu 1a01000.display-controller: [drm] refcount=1 [ 52.507981] msm_dpu 1a01000.display-controller: [drm] start=00100001 [ 52.507989] msm_dpu 1a01000.display-controller: [drm] size=8355840 [ 52.507996] msm_dpu 1a01000.display-controller: [drm] imported=no [ 52.508005] msm_dpu 1a01000.display-controller: [drm] crtc-pos=1080x1920+0+0 [ 52.508014] msm_dpu 1a01000.display-controller: [drm] src-pos=1080.000000x1920.000000+0.000000+0.000000 [ 52.508026] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.508033] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.508040] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.508047] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.508054] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.508061] msm_dpu 1a01000.display-controller: [drm] stage=1 [ 52.508068] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_0 [ 52.508075] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.508082] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.508089] msm_dpu 1a01000.display-controller: [drm] src[0]=1080x1920+0+0 [ 52.508098] msm_dpu 1a01000.display-controller: [drm] dst[0]=1080x1920+0+0 [ 52.508108] msm_dpu 1a01000.display-controller: [drm] plane[39]: plane-1 [ 52.508115] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.508121] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.508128] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.508136] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.508147] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.508154] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.508160] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.508167] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.508173] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.508180] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.508186] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_1 [ 52.508193] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.508200] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.508206] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.508215] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.508223] msm_dpu 1a01000.display-controller: [drm] plane[45]: plane-2 [ 52.508230] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.508236] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.508243] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.508251] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.508262] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.508269] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.508275] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.508282] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.508289] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.508295] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.508302] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_4 [ 52.508308] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.508315] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.508321] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.508329] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.508338] msm_dpu 1a01000.display-controller: [drm] plane[51]: plane-3 [ 52.508345] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.508351] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.508357] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.508366] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.508377] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.508384] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.508390] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.508397] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.508404] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.508410] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.508417] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_5 [ 52.508423] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.508430] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.508437] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.508445] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.508453] msm_dpu 1a01000.display-controller: [drm] plane[57]: plane-4 [ 52.508460] msm_dpu 1a01000.display-controller: [drm] crtc=(null) [ 52.508467] msm_dpu 1a01000.display-controller: [drm] fb=0 [ 52.508473] msm_dpu 1a01000.display-controller: [drm] crtc-pos=0x0+0+0 [ 52.508481] msm_dpu 1a01000.display-controller: [drm] src-pos=0.000000x0.000000+0.000000+0.000000 [ 52.508493] msm_dpu 1a01000.display-controller: [drm] rotation=1 [ 52.508499] msm_dpu 1a01000.display-controller: [drm] normalized-zpos=0 [ 52.508506] msm_dpu 1a01000.display-controller: [drm] color-encoding=ITU-R BT.601 YCbCr [ 52.508512] msm_dpu 1a01000.display-controller: [drm] color-range=YCbCr limited range [ 52.508519] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.508525] msm_dpu 1a01000.display-controller: [drm] stage=0 [ 52.508532] msm_dpu 1a01000.display-controller: [drm] sspp[0]=sspp_8 [ 52.508538] msm_dpu 1a01000.display-controller: [drm] multirect_mode[0]=none [ 52.508545] msm_dpu 1a01000.display-controller: [drm] multirect_index[0]=solo [ 52.508552] msm_dpu 1a01000.display-controller: [drm] src[0]=0x0+0+0 [ 52.508560] msm_dpu 1a01000.display-controller: [drm] dst[0]=0x0+0+0 [ 52.508568] msm_dpu 1a01000.display-controller: [drm] crtc[63]: crtc-0 [ 52.508576] msm_dpu 1a01000.display-controller: [drm] enable=1 [ 52.508582] msm_dpu 1a01000.display-controller: [drm] active=1 [ 52.508588] msm_dpu 1a01000.display-controller: [drm] self_refresh_active=0 [ 52.508595] msm_dpu 1a01000.display-controller: [drm] planes_changed=0 [ 52.508602] msm_dpu 1a01000.display-controller: [drm] mode_changed=0 [ 52.508609] msm_dpu 1a01000.display-controller: [drm] active_changed=0 [ 52.508615] msm_dpu 1a01000.display-controller: [drm] connectors_changed=0 [ 52.508622] msm_dpu 1a01000.display-controller: [drm] color_mgmt_changed=0 [ 52.508628] msm_dpu 1a01000.display-controller: [drm] plane_mask=1 [ 52.508635] msm_dpu 1a01000.display-controller: [drm] connector_mask=1 [ 52.508642] msm_dpu 1a01000.display-controller: [drm] encoder_mask=1 [ 52.508649] msm_dpu 1a01000.display-controller: [drm] mode: "1080x1920": 60 133627 1080 1120 1128 1148 1920 1928 1930 1940 0x48 0x0 [ 52.508665] msm_dpu 1a01000.display-controller: [drm] lm[0]=0 [ 52.508673] msm_dpu 1a01000.display-controller: [drm] ctl[0]=0 [ 52.508681] msm_dpu 1a01000.display-controller: [drm] connector[32]: DSI-1 [ 52.508688] msm_dpu 1a01000.display-controller: [drm] crtc=crtc-0 [ 52.508695] msm_dpu 1a01000.display-controller: [drm] self_refresh_aware=0 [ 52.508702] msm_dpu 1a01000.display-controller: [drm] max_requested_bpc=0 [ 52.508709] msm_dpu 1a01000.display-controller: [drm] colorspace=Default [ 52.508717] msm_dpu 1a01000.display-controller: [drm:drm_atomic_check_only] checking 0000000013d4471b [ 52.508737] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1] [ 52.508755] msm_dpu 1a01000.display-controller: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:63:crtc-0] [ 52.508772] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000013d4471b [ 52.508789] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 00000000f2e1447b state 00000000b2f70dc9 to 0000000013d4471b [ 52.508801] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000013d4471b [ 52.508819] [drm:dpu_encoder_virt_atomic_check] enc31 [ 52.508831] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_private_obj_state] Added new private object 000000001feccef9 state 00000000c8bd6774 to 0000000013d4471b [ 52.508854] [drm:dpu_crtc_atomic_check] crtc63: check [ 52.508869] [drm:dpu_core_perf_crtc_check] crtc=63 clk_rate=131997600 core_ib=800000 core_ab=502848000 [ 52.508885] [drm:dpu_core_perf_crtc_check] calculated bandwidth=502848k [ 52.508895] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 5700000 [ 52.508913] msm_dpu 1a01000.display-controller: [drm:drm_atomic_commit] committing 0000000013d4471b [ 52.508929] [drm:dpu_plane_prepare_fb] plane33 FB[64] [ 52.508945] msm_dpu 1a01000.display-controller: [drm:msm_framebuffer_prepare] FB[64]: iova[0]: 00002000 (0) [ 52.508966] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.508981] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1524)@ 52.502813 -> 52.489721 [e 13 us, 0 rep] [ 52.509009] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.509022] msm_dpu 1a01000.display-controller: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1529)@ 52.502856 -> 52.489720 [e 11 us, 0 rep] [ 52.509048] DPU:KMS: dpu_kms_enable_commit [ 52.509052] DPU:KMS: dpu_kms_wait_flush [ 52.509054] DPU:KMS: dpu_kms_wait_for_commit_done [ 52.509057] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 52.509066] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.509078] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.538316] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 52.538443] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:52532162896 [ 52.562649] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.562666] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.562677] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 52.562684] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 52.562696] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: hwmode: htotal 1148, vtotal 1940, vdisplay 1920 [ 52.562715] msm_dpu 1a01000.display-controller: [drm:drm_calc_timestamping_constants] crtc 63: clock 133627 kHz framedur 16666691 linedur 8591 [ 52.562733] [drm:dpu_crtc_atomic_begin] crtc63 [ 52.562747] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.562759] [drm:_dpu_crtc_blend_setup] crtc63 [ 52.562772] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x0] <= 0x0 [ 52.562785] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x40] <= 0x0 [ 52.562796] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x70] <= 0x0 [ 52.562808] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA0] <= 0x0 [ 52.562820] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(mixer_id):0x4] <= 0x0 [ 52.562831] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(mixer_id):0x44] <= 0x0 [ 52.562843] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(mixer_id):0x74] <= 0x0 [ 52.562855] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(mixer_id):0xA4] <= 0x0 [ 52.562867] [drm:dpu_reg_write] *ERROR* [CTL_FETCH_PIPE_ACTIVE:0xFC] <= 0x0 [ 52.562881] [drm:_dpu_crtc_blend_setup_pipe.isra.0] crtc 63 stage:1 - plane 33 sspp 1 fb 64 multirect_idx 0 [ 52.562898] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_FG_ALPHA + stage_off:0x24] <= 0xFF [ 52.562911] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_BG_ALPHA + stage_off:0x28] <= 0x0 [ 52.562923] [drm:dpu_reg_write] *ERROR* [LM_BLEND0_OP + stage_off:0x20] <= 0x100 [ 52.562935] [drm:_dpu_crtc_blend_setup] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100 [ 52.562953] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 52.562964] [drm:dpu_reg_write] *ERROR* [LM_OUT_SIZE:0x4] <= 0x7800438 [ 52.562976] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 52.562988] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x0] [ 52.562998] [drm:dpu_reg_write] *ERROR* [LM_OP_MODE:0x0] <= 0x2 [ 52.563010] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0 [ 52.563025] [drm:dpu_reg_write] *ERROR* [CTL_LAYER(lm):0x0] <= 0x1000002 [ 52.563036] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT(lm):0x40] <= 0x0 [ 52.563048] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT2(lm):0x70] <= 0x0 [ 52.563060] [drm:dpu_reg_write] *ERROR* [CTL_LAYER_EXT3(lm):0xA0] <= 0x0 [ 52.563072] [drm:dpu_plane_atomic_update] plane33 [ 52.563084] [drm:dpu_plane_atomic_update] plane33 FB[64] 1080.000000x1920.000000+0.000000+0.000000->crtc63 1080x1920+0+0, XR24 ubwc 0 [ 52.563105] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x14] <= 0x2000 [ 52.563118] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x18] <= 0x0 [ 52.563129] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x1C] <= 0x0 [ 52.563141] [drm:dpu_reg_write] *ERROR* [SSPP_SRC0_ADDR + i * 0x4:0x20] <= 0x0 [ 52.563154] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE0:0x24] <= 0x1100 [ 52.563166] [drm:dpu_reg_write] *ERROR* [SSPP_SRC_YSTRIDE1:0x28] <= 0x0 [ 52.563178] [drm:dpu_reg_write] *ERROR* [src_size_off:0x0] <= 0x7800438 [ 52.563190] [drm:dpu_reg_write] *ERROR* [src_xy_off:0x8] <= 0x0 [ 52.563201] [drm:dpu_reg_write] *ERROR* [out_size_off:0xC] <= 0x7800438 [ 52.563213] [drm:dpu_reg_write] *ERROR* [out_xy_off:0x10] <= 0x0 [ 52.563228] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_LR:0x100] <= 0x0 [ 52.563241] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_TB:0x104] <= 0x0 [ 52.563253] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C0_REQ_PIXELS:0x108] <= 0x7800438 [ 52.563265] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_LR:0x110] <= 0x0 [ 52.563277] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_TB:0x114] <= 0x0 [ 52.563289] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS:0x118] <= 0x7800438 [ 52.563301] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_LR:0x120] <= 0x0 [ 52.563313] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_TB:0x124] <= 0x0 [ 52.563325] [drm:dpu_reg_write] *ERROR* [SSPP_SW_PIX_EXT_C3_REQ_PIXELS:0x128] <= 0x7800438 [ 52.563339] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x38] [ 52.563351] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x200] [ 52.563361] [drm:dpu_reg_write] *ERROR* [sblk->scaler_blk.base + SSPP_VIG_OP_MODE:0x200] <= 0x0 [ 52.563374] [drm:dpu_reg_write] *ERROR* [format_off:0x30] <= 0x236FF [ 52.563386] [drm:dpu_reg_write] *ERROR* [unpack_pat_off:0x34] <= 0x3020001 [ 52.563397] [drm:dpu_reg_write] *ERROR* [op_mode_off:0x38] <= 0x80000000 [ 52.563411] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 52.563421] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x1 [ 52.563436] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0xB0] [ 52.563448] [drm:dpu_vbif_set_ot_limit] VBIF_RT xin:0 ot_lim:0 [ 52.563457] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x2AC] [ 52.563468] [drm:dpu_reg_write] *ERROR* [clk_ctrl_reg->reg_off:0x2AC] <= 0x0 [ 52.563482] [drm:dpu_crtc_atomic_flush] crtc63 [ 52.563494] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 52.563512] DPU:KMS: dpu_kms_flush_commit [ 52.563516] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.563527] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.563606] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.563684] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.563762] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.563839] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.563917] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.563994] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564070] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564147] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564224] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564301] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564378] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564454] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564531] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564608] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564684] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564760] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564837] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564914] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.564990] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.565068] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.565144] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.565221] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.565297] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.565373] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.565451] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.565527] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x30] [ 52.565603] hw recovery is not complete for ctl:1 [ 52.565609] [drm:dpu_encoder_phys_vid_prepare_for_kickoff:531] [dpu error]enc31 intf1 ctl 1 reset failure: -22 [ 52.565626] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state [ 52.565637] [drm:dpu_crtc_commit_kickoff] crtc63 first commit [ 52.565645] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x190] [ 52.565656] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x194] [ 52.565667] [drm:dpu_reg_write] *ERROR* [VBIF_XIN_CLR_ERR:0x19C] <= 0x0 [ 52.565682] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.565692] [drm:dpu_reg_write] *ERROR* [CTL_FLUSH:0x18] <= 0x20041 [ 52.565706] DPU:KMS: dpu_kms_wait_flush [ 52.565708] DPU:KMS: dpu_kms_wait_for_commit_done [ 52.565711] [drm:dpu_encoder_wait_for_commit_done] enc31 [ 52.565719] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.565730] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.565934] DPU:KMS: mdp_snapshot: START [ 52.566854] DPU:KMS: mdp_snapshot: DONE [ 52.618555] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.618575] [drm:dpu_reg_read] *ERROR* [dpu_reg_read:0x18] [ 52.618586] [drm:dpu_encoder_phys_vid_wait_for_commit_done:505] [dpu error]vblank timeout: 20041 [ 52.618593] [drm:dpu_kms_wait_for_commit_done:485] [dpu error]wait for commit done returned -110 [ 52.618600] DPU:KMS: dpu_kms_complete_comit [ 52.618603] [drm:dpu_core_perf_crtc_update] crtc:63 enabled:1 core_clk:131997600 [ 52.618618] [drm:dpu_crtc_complete_commit] crtc63: send event: 00000000716f723b [ 52.618634] [drm:dpu_plane_cleanup_fb] plane33 FB[64] [ 52.618654] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 0000000013d4471b [ 52.618665] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.618674] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 52.618682] [drm:dpu_crtc_destroy_state] crtc63 [ 52.618694] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 52.618703] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 52.618718] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 0000000013d4471b [ 52.618792] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 000000009958c70e [ 52.618805] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 52.618813] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 000000000e3c0e61 state to 000000009958c70e [ 52.618826] [drm:dpu_plane_duplicate_state] plane33 [ 52.618833] [drm:drm_mode_object_get] OBJ ID: 64 (3) [ 52.618839] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 000000004fc13beb state to 000000009958c70e [ 52.618851] [drm:dpu_plane_duplicate_state] plane39 [ 52.618857] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000008f19c61d state to 000000009958c70e [ 52.618869] [drm:dpu_plane_duplicate_state] plane45 [ 52.618875] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:45:plane-2] 00000000b634428e state to 000000009958c70e [ 52.618886] [drm:dpu_plane_duplicate_state] plane51 [ 52.618891] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:51:plane-3] 000000003f74cf12 state to 000000009958c70e [ 52.618902] [drm:dpu_plane_duplicate_state] plane57 [ 52.618908] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_plane_state] Added [PLANE:57:plane-4] 000000000b483c46 state to 000000009958c70e [ 52.618920] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 52.618925] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 52.618931] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000a86eb5ab state to 000000009958c70e [ 52.618944] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 000000009958c70e [ 52.618951] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 52.618956] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 52.618961] [drm:dpu_crtc_destroy_state] crtc63 [ 52.618969] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 52.618975] [drm:drm_mode_object_put.part.0] OBJ ID: 64 (4) [ 52.618980] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 000000009958c70e [ 52.654578] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [ 52.654769] [drm:dpu_crtc_frame_event_work] crtc63 event:2 ts:52648440709 [ 53.314349] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_init] Allocated atomic state 00000000968f3705 [ 53.314391] [drm:drm_mode_object_get] OBJ ID: 65 (2) [ 53.314405] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_crtc_state] Added [CRTC:63:crtc-0] 00000000fc59698d state to 00000000968f3705 [ 53.314427] msm_dpu 1a01000.display-controller: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:63:crtc-0] to 00000000968f3705 [ 53.314446] [drm:drm_mode_object_get] OBJ ID: 32 (6) [ 53.314455] [drm:drm_mode_object_get] OBJ ID: 32 (7) [ 53.314465] msm_dpu 1a01000.display-controller: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000fc56f0d3 state to 00000000968f3705 [ 53.314482] msm_dpu 1a01000.display-controller: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000968f3705 [ 53.314494] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (7) [ 53.314504] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6) [ 53.314513] [drm:dpu_crtc_destroy_state] crtc63 [ 53.314527] [drm:drm_mode_object_put.part.0] OBJ ID: 65 (3) [ 53.314539] msm_dpu 1a01000.display-controller: [drm:__drm_atomic_state_free] Freeing atomic state 00000000968f3705 leeco-s2-mainline:~$