```
	if (data->q6afe_clk_ver == Q6AFE_CLK_V1 &&
	    data->dig_cdc_mclk_en) {
		ret = snd_soc_dai_set_sysclk(cpu_dai,  LPAIF_DIG_CLK, DEFAULT_MCLK_RATE, 0);
		if (ret)
			dev_err(card->dev, "Failed to enable LPAIF dig clk: %d\n", ret);
		}

```
last } should be at same position like if?